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WM9714CLGEFL/RV Datasheet(PDF) 16 Page - Cirrus Logic |
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WM9714CLGEFL/RV Datasheet(HTML) 16 Page - Cirrus Logic |
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16 / 120 page  WM9714L 16 Rev 4.0 PCM AUDIO INTERFACE TIMING – MASTER MODE PCMCLK (Output) PCMADC PCMFS (Output) tDL PCMDAC tDDA tDHT tDST Figure 8 Digital Audio Data Timing – Master Mode (see Control Interface) Test Conditions DBVDD = 3.3V, DCVDD = 3.3V, DGND1 = DGND2 = 0V, TA = -25C to +85C, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information PCMFS propagation delay from PCMCLK falling edge tDL 10 ns PCMADC propagation delay from PCMCLK falling edge tDDA 10 ns PCMDAC setup time to PCMCLK rising edge tDST 10 ns PCMDAC hold time from PCMCLK rising edge tDHT 10 ns |
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