25 / 64 page
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *D
Page 25 of 64
CY37064
CY37128
Typical 5.0V Power Consumption (continued)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
0
10
20
30
40
50
60
70
80
90
0
2 0
4 0
6 0
8 0
100
1 2 0
1 4 0
160
1 8 0
Frequency (M H z )
L o w P o we r
H ig h S pee d
0
20
40
60
80
100
120
140
160
0
2 0
4 0
6 0
8 0
100
120
140
160
180
Freque ncy (M H z )
Lo w P o w e r
H igh S p e e d
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
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