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Ultra37000 CPLD Family
Document #: 38-03007 Rev. *D
Page 31 of 64
CY37512V
Typical 3.3V Power Consumption (continued)
0
50
10 0
15 0
20 0
25 0
0
1 0
2 03 0
4 05 0
6 07 0
8 09 0
F r e que nc y ( M H z )
Low P o w e r
H ig h S peed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
Pin Configurations[20]
44-pin TQFP (A44)
Top View
I/O27/TDI
I/O26
I/O25
I/O24
CLK1/I4
GND
I3
CLK3/I2
I/O23
I/O22
I/O21
I/O5/TCK
I/O6
I/O7
CLK2/I0
GND
CLK0/I1
I/O8
I/O9
I/O10
I/O11
8
9
7
10
11
3
4
2
5
6
1
18 19 20
22
21
13 14 15
17
16
12
31
30
29
32
33
26
25
24
27
28
23
44 43 42
40
41
39 38 37
35
36
34
JTAGEN