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GS3471 Datasheet(PDF) 97 Page - Semtech Corporation |
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GS3471 Datasheet(HTML) 97 Page - Semtech Corporation |
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97 / 179 page  GS3471 Final Data Sheet Rev.4 PDS-060498 September 2017 97 of 179 Semtech www.semtech.com Table 4-28: GSPI Timing Parameters Parameter Symbol Equivalent SCLK Cycles Min Typ Max Units Time to GSPI ready after power up/reset t_GSPI_ready —500 — μs CS low before SCLK rising edge t0 2.7 — 22 ns SCLK frequency — — 22 MHz SCLK period t1 45 — — ns SCLK duty cycle t2 40 50 60 % Input data setup time t3 1.8 — — ns SCLK idle time - write t4 145 — — ns SCLK idle time - read t5 4 161 — — ns Inter-command delay time tcmd 4 161 — — ns SDOUT after SCLK falling edge t6 —— 9.1 ns CS high after final SCLK falling edge t7 0.0 — — ns Input data hold time t8 1.1 — — ns CS high time t9 45 — — ns SDIN to SDOUT combinational delay —— 7.4 ns Max. chips daisy chained at max SCLK frequency When host clocks in SDOUT data on rising edge of SCLK —— 1 GS3471 chips Max. frequency for 32 daisy-chained devices —— 1.5 MHz Max. chips daisy-chained at max. SCLK frequency When host clocks in SDOUT data on falling edge of SCLK —— 5 GS3471 chips Max. frequency for 32 daisy-chained devices —— 3.5 MHz Note: 1. tcmd_GSPI_conf inter-command delay must be used whenever modifying HOST_CONFIG register at address 0x00 |
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