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ACT88326VA Datasheet(PDF) 18 Page - Active-Semi, Inc |
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ACT88326VA Datasheet(HTML) 18 Page - Active-Semi, Inc |
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18 / 41 page ![]() ACT88326VA Rev 1.0, 29-May-2018 Innovative PowerTM www.active-semi.com ActiveSwitcherTM is a trademark of Active-Semi. Copyright © 2018 Active-Semi, Inc 18 Table 1a. SLEEP Mode Truth Table (SLEEP MODE bit is configured to 0) Table 1b. SLEEP Mode Truth Table (SLEEP MODE bit is configured to 1) DPSLP State The DPSLP state is another low power operating mode for the operating system. It is intended to be used in a lower power configuration than the SLEEP mode. It is similar to the SLEEP state, but DPSLP uses slightly dif- ferent configurations to enter and exit this mode. Each output can be programmed to be on or off in the DPSLP state. This programming can be different and independ- ent from the SLEEP state. The outputs follow their pro- grammed sequencing delay times when turning on or off as they enter or exit the DPSLP state. The IC can enter DPSLP state via I2C register bit DPSLP, I2C register bit DPSLP MODE, and a GPIO in- put pin. The IC’s specific CMI determines the specific combination of these three inputs to enter DPSLP state. The I2C bit DPSLP MODE is set at factory and cannot be changed by the user. It controls the logical combina- tion of the GPIO input and the DPSLP register bit to en- ter DPSLP state. When DPSLP MODE is factory configured to 1, the log- ical combination is an “OR” function and when DPSLP is factory configured to a 0, the logical combination is an “AND” function. If no GPIOs are configured as a control input to enter and exit DPSLP state then only the DPSLP register bit controls the entry and exit of the DPSLP state. Table 2a and 2b show the conditions to enter DPSLP state. ACT88326’s I2C stays enabled in DPSLP state. The IC exits the DPSLP state when the conditions to enter DPSLP state are no longer present. Asserting nPB low for > 32ms clears the DPSLP bit to 0 and the PMIC exits DPSLP state. Table 2a. DPSLP Mode Truth Table (DPSLP MODE factory bit is configured to 0) Table 2b. DPSLP Mode Truth Table (DPSLP MODE factory bit is configured to 1) |
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