ACT88326VA datasheet(21/41 Pages) ACTIVE-SEMI

21 / 41 page

ACT88326VA

Rev 1.0, 29-May-2018

Innovative PowerTM

www.active-semi.com

ActiveSwitcherTM is a trademark of Active-Semi.

DVS can be implemented for all buck converters at one

time via I2C. The user can select from two different

configurations to enter DVS via I2C. Note that DVS is

disabled when EN_DVS_I2C = 0.

1. Enable DVS via a single I2C write to

I2C_DVS_ON bit: With EN_DVS_I2C = 1

and SEL_DVS_IN = 0, the IC enters DVS

when I2C_DVS_ON = 1 and exits DVS

when it equals 0.

2. Enable DVS whenever the IC enters

SLEEP state: With EN_DVS_I2C = 1 and

SEL_DVS_IN = 1, any condition that puts

the IC into SLEEP state also puts the IC

into DVS mode. Note that I2C_DVS_ON bit

does not affect this configuration.

Note that the IC cannot be configured to enter DVS in

DPSLP state. Table 3 summarizes I2C DVS functionality.

EN_DVS_I2C

SEL_DVS_IN

I2C_DVS_ON

DVS MODE

Off

On in SLEEP

state

Table 3. I2C DVS Control

For fault free operation, the user must ensure output

load conditions plus the current required to charge the

output capacitance during a DVS rising voltage

condition does not exceed the current limit setting of the

regulator. As with any power supply, changing an output

voltage too fast can require a current higher than the

current limit setting. The user must ensure that the

voltage step, slew rate, and load current conditions do

not result in an instantaneous loading that results in a

current limit condition.

Input Voltage Monitoring (SYSMON)

The ACT88326 monitors the input voltage on the VINx

pins to ensure it is within specified limits for system level

operation. The IC “wakes up” and allows I2C communi-

cation when VINx rises above UVLO (~2.7V). However,

the outputs do not turn on until VINx rises above the

SYSMON threshold. SYSMON is programmable be-

tween 2.7V and 4.2V. The IC then asserts the nIRQ pin

if VINx drops below SYSMON, but the outputs continue

to operate normally. The IC turns off all outputs if the

input voltage drops below UVLO. I2C bit VSYSSTAT =

1 when VINx < SYSMON and 0 when VINx > SYSMON.

This fault can be masked with I2C bit VSYSMSK.

Fault Protection

The ACT88326 contains several levels of fault protec-

tion, including the following:

Output Overvoltage

Output Undervoltage

Output Current Limit and short circuit

Thermal Warning

Thermal Shutdown

There are three types of I2C register bits associated with

each fault condition: fault flag bits, fault bits, and mask

bits. The fault flag bits display the real-time fault status.

Their status is valid regardless of whether or not that

fault is masked. The mask bits either block or allow the

fault to affect the fault bit. Each potential fault condition

can be masked via I2C if desired. Any unmasked fault

condition results in the fault bit going high, which asserts

the nIRQ pin. nIRQ is typically active low. The nIRQ pin

only de-asserts after the fault condition is no longer pre-

sent and the corresponding fault bit is read via I2C. Note

that masked faults can still be read in the fault flag bit.

Refer to Active-Semi Application Note describing the

gramming ranges.

nIRQ (Interrupt)

The interrupt function is typically used to drive the inter-

rupt input of the system processor. Many of the

ACT88326's functions support interrupt-generation as a

result of various conditions. These are typically masked

by default, but may be unmasked via the I2C interface.

For more information about the available fault condi-

tions, refer to the appropriate sections of this datasheet.

nIRQ can be triggered from:

1. Die temperature warning generated

2. Any buck regulator exceeding peak current limit

for 16 cycles after soft start or a UV/OV condi-

tion.

3. Any LDO regulator exceeding current limit for

more than 16uS after soft start or a UV/OV con-

dition.

4. Input goes above OVP threshold or falls below

the UV threshold.

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