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VSC8504-02 Datasheet(PDF) 50 Page - Microsemi Corporation

Part # VSC8504-02
Description  Quad-Port 10/100/1000BASE-T PHY with Synchronous Ethernet and QSGMII/SGMII MAC
PDF  131 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

VSC8504-02 Datasheet(HTML) 50 Page - Microsemi Corporation

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Functional Descriptions
VMDS-10507 VSC8504-02 Datasheet Revision 4.2
39
The following tables provide information about the IDCODE and USERCODE binary values stored in the
device JTAG registers.
The following table provides information about the location and IEEE compliance of the JTAG instruction
codes used in the VSC8504-02. Instructions not explicitly listed in the table are reserved. For more
information about these IEEE specifications, visit the IEEE Web site at www.IEEE.org.
HIGHZ
Places the component in a state in which all of its system logic
outputs are placed in a high-impedance state. In this state, an in-
circuit test system can drive signals onto the connections normally
driven by a component output without incurring a risk of damage to
the component. This makes it possible to use a board where not
all of the components are compatible with the IEEE 1149.1
standard.
IDCODE
Provides the version number (bits 31:28), device family ID (bits
27:12), and the manufacturer identity (bits 11:1) to be serially read
from the device.
SAMPLE/PRELOA
D
Allows a snapshot of inputs and outputs during normal system
operation to be taken and examined. It also allows data values to
be loaded into the boundary scan cells prior to the selection of
other boundary scan test instructions.
USERCODE
Provides the version number (bits 31:28), part number (bits 27:12),
and the manufacturer identity (bits 11:1) to be serially read from
the device.
Table 13 •
IDCODE JTAG Device Identification Register Descriptions
Description
Device Version
Family ID
Manufacturing Identity
LSB
Bit field
31–28
27–12
11–1
0
Binary value
0000
1000 0101 0111 0100
000 0111 0100
1
Table 14 •
USERCODE JTAG Device Identification Register Descriptions
Description
Device Version
Model Number
Manufacturing Identity
LSB
Bit field
31–28
27–12
11–1
0
Binary value
0010
1000 0101 0111 0100
000 0111 0100
1
Table 15 •
JTAG Instruction Code IEEE Compliance
Instruction
Code
Selected Register
Register
Width
IEEE 1149.1
EXTEST
6'b000000
Boundary Scan
161
Mandatory
SAMPLE/PRELOA
D
6'b000001
Boundary Scan
161
Mandatory
IDCODE
6'b100000
Device Identification
32
Optional
USERCODE
6'b100101
Device Identification
32
Optional
CLAMP
6'b000010
Bypass Register
1
Optional
HIGHZ
6'b000101
Bypass Register
1
Optional
BYPASS
6'b111111
Bypass Register
1
Mandatory
Table 12 •
JTAG Instruction Codes (continued)
Instruction Code
Description



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