VSC8504-02 datasheet(93/131 Pages) MICROSEMI

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Registers

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

4.6.10

Two-Wire Serial MUX Control 2

devices.

4.6.11

Two-Wire Serial MUX Data Read/Write

4.6.12

Recovered Clock 1 Control

signal.

Table 83 •

Two-Wire Serial MUX Interface Status and Control, Address 21G (0x15)

Bit

Name

Access Description

Default

Two-wire serial MUX

ready

1: Two-wire serial MUX is ready for read or

write

14:12 Reserved

Reserved

11:10

PHY port Address

R/W

Specific VSC8504-02 PHY port being

addressed.

Enable two-wire serial

MUX access

R/W

Self-clearing bit.

1: Execute read or write through the two-wire

serial MUX based on the settings of register

bit 21G.8

Two-wire serial MUX

read or write

R/W

1: Read from two-wire serial MUX

0: Write to two-wire serial MUX

7:0

Two-wire serial MUX

address

R/W

Sets the address of the two-wire serial MUX

used to direct read or write operations.

0x00

Table 84 •

Two-Wire Serial MUX Data Read/Write, Address 22G (0x16)

Bit

Name

Access Description

Default

15:8 Two-wire serial MUX

read data

Eight-bit data read from two-wire serial MUX;

requires setting both register 21G.9 and 21G.8 to

7:0

Two-wire serial MUX

write data

R/W

Eight-bit data to be written to two-wire serial MUX. 0x00

Table 85 •

Recovered Clock 1 Control, Address 23G (0x17)

Bit

Name

Access Description

Default

Enable

RCVRDCLK1

R/W

1: Enable recovered clock 1 output

0: Disable recovered clock 1 output

14:11

Clock source select R/W

Select bits for source PHY for recovered clock:

0000: PHY0

0001: PHY1

0010: PHY2

0011: PHY3

0100–1111: Reserved

0000

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