VSC8504-02 datasheet(56/131 Pages) MICROSEMI

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Registers

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

4.2.1

Mode Control

The device register at memory address 0 controls several aspects of VSC8504-02 functionality. The

following table shows the available bit settings in this register and what they control.

Reserved

Auxiliary control and status

LED mode select

LED behavior

Extended register page access

Table 18 •

Mode Control, Address 0 (0x00)

Bit Name

Access Description

Default

Software reset

R/W

Self-clearing. Restores all serial management

interface (SMI) registers to default state,

except for sticky and super-sticky bits.

1: Reset asserted.

0: Reset de-asserted. Wait [X] after setting this

bit to initiate another SMI register access.

Loopback

R/W

1: Loopback enabled.

0: Loopback disabled. When loop back is

enabled, the device functions at the current

speed setting and with the current duplex

mode setting (bits 6, 8, and 13 of this register).

Forced speed selection

LSB

R/W

Least significant bit. MSB is bit 6.

00: 10 Mbps.

01: 100 Mbps.

10: 1000 Mbps.

11: Reserved.

Autonegotiation enable

R/W

1: Autonegotiation enabled.

0: Autonegotiation disabled.

Power-down

R/W

1: Power-down enabled.

Isolate

R/W

1: Disconnect the MAC-side interface of the

device from the rest of the datapath. Traffic

entering the PHY from either the MAC-side or

media-side interface will terminate inside the

PHY.

Restart autonegotiation

R/W

Self-clearing bit.

1: Restart autonegotiation on media interface.

Duplex

R/W

1: Full-duplex.

0: Half-duplex.

Collision test enable

R/W

1: Collision test enabled.

Forced speed selection

MSB

R/W

Most significant bit. LSB is bit 13.(1)

00: 10 Mbps.

01: 100 Mbps.

10: 1000 Mbps.

11: Reserved.

Table 17 •

Main Registers (continued)

Address Name

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