EM78P451SWM datasheet(27/54 Pages) EMC

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EM78P451S

8-Bit Microcontroller with OTP ROM

Product Specification (V1.0) 06.01.2004

• 23

(This specification is subject to change without further notice)

Bit 2~0 (S BRS):SPI Baud Rate Select Bits

SBRS2 (Bit 2)

SBRS1 (Bit 1)

SBRS0 (Bit 0)

Mode

Baud Rate

Master

Fsco/2

Master

Fsco/4

Master

Fsco/8

Master

Fsco/16

Master

Fsco/32

Slave

/SS enable

Slave

/SS disable

Master

TMR1/2

NOTE

In master mode, /SS is disable.

INTC: Interrupt control register

Bit 3 (TM1IE) TM1IE interrupt enable bit.

0: disable TM1IE interrupt

1: enable TM1IE interrupt

Bit 2 (SPIIE) SPI interrupt enable bit.

0: disable SPI interrupt

1: enable SPI interrupt

Bit 1 (EXIE) EXIF interrupt enable bit.

0: disable EXIF interrupt

1: enable EXIF interrupt

Bit 0 (TCIE) TCIF interrupt enable bit.

0: disable TCIF interrupt

1: enable TCIF interrupt

Table 3 Related Status/Data Registers of the SPI Mode

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0X0A

SPIRB/RA

SRB7

SRB6

SRB5

SRB4

SRB3

SRB2

SRB1

SRB0

0x0B

SPIWB/RB

SWB7

SWB6

SWB5

SWB4

SWB3

SWB2

SWB1

SWB0

0x0C

SPIS/RC

TM1IF

OD3

OD4

RBFIF

RBF

SPIRB: SPI Read Buffer. Once the serial data is received completely, it will load to

SPIRB from SPISR. The RBF bit and the RBFIF bit in the SPIS register will be

set also.

SPIWB: SPI Write Buffer. As a transmitted data is loaded, the SPIS register stands by

and start to shift the data when sensing SCK edge with SSE set to “1”.

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