EM78P451SWM datasheet(28/54 Pages) EMC

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EM78P451S

8-Bit Microcontroller with OTP ROM

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Product Specification (V1.0) 06.01.2004

(This specification is subject to change without further notice)

SPIS: SPI Status register

Bit 4 (TM1IF):Timer1 interrupt flag.

Bit 3 (OD3)Open-Drain Control bit (P93)

0 = Open-drain disable for SDO.

1 = Open-drain enable for SDO,

Bit 2 (OD4):Open Drain-Control bit (P94)

0 = Open-drain disable for SCK.

1 = Open-drain enable for SCK

Bit 1 (RBFIF):Read Buffer Full Interrupt flag

1 = Receive is completed, SPIB is full, and an interrupt occurs if enabled.

0 = Receive is ongoing, SPIB is empty.

Bit 0 (RBF):Read Buffer Full flag

0 = Receive is ongoingt, SPIB is empty.

1 = Receive is completed, SPIB is full.

4.5.5 SPI Mode Timing

The edge of SCK is selected by programming bit CES. The waveform shown in Fig.13

is applicable regardless of whether the EM78P451S is under master or slave mode

with /SS disabled. However, The waveform in Fig. 14 can only be implemented in slave

mode with /SS enabled.

Fig. 13 SPI Mode with /SS Disable

EM78P451SWM Datasheet(PDF) 28 Page - ELAN Microelectronics Corp