| Electronic Components Datasheet Search |
|
XRT75VL00D Datasheet(PDF) 84 Page - Exar Corporation |
|
|
|||||||||||||||||||||||||||||
XRT75VL00D Datasheet(HTML) 84 Page - Exar Corporation |
|
84 / 92 page ![]() XRT75VL00D E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3 79 • If the LIU has been configured to operate in the Hardware Mode. Then the user should tie pin 43 (JATx/JARx*) to "1". e. Enable the "SONET APS Recovery Time" Mode Finally, if the user intends to use the LIU in an Application that is required to reacquire proper SONET and DS3 traffic, prior within 50ms of an APS (Automatic Protection Switching) event (per Telcordia GR-253-CORE), then the user should set Bit 4 (SONET APS Recovery Time Disable), within the "Jitter Attenuator Control" Register, to "0" as depicted below. NOTES: 1. The ability to disable the "SONET APS Recovery Time" mode is only available if the LIU is operating in the Host Mode. If the LIU is operating in the "Hardware" Mode, then this "SONET APS Recovery Time Mode" feature will always be enabled. 2. The "SONET APS Recovery Time" mode will be discussed in greater detail in “Section 9.8.3, How does the LIU permit the user to comply with the SONET APS Recovery Time requirements of 50ms (per Telcordia GR-253- CORE)?” on page 83. 9.8.2 Recommendations on Pre-Processing the Gapped Clocks (from the Mapper/ASIC Device) prior to routing this DS3 Clock and Data-Signals to the Transmit Inputs of the LIU In order to minimize the effects of "Clock-Gapping" Jitter within the DS3 signal that is ultimately transmitted to the DS3 Line (or facility), we recommend that some "pre-processing" of the "Data-Signals" and "Clock-Signals" (which are output from the Mapper device) be implemented prior to routing these signals to the "Transmit Inputs" of the LIU. 9.8.2.1 SOME NOTES PRIOR TO STARTING THIS DISCUSSION: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 CHANNEL 1 ADDRESS LOCATION = 0X0F CHANNEL 2 ADDRESS LOCATION = 0X17 BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2 BIT 1BIT 0 Unused SONET APS Recovery Time DisableCh_n JA RESET Ch_n JA1 Ch_n JA in Tx Path Ch_n JA0 Ch_n R/O R/O R/O R/W R/W R/W R/W R/W 00 000 0 11 JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 CHANNEL 1 ADDRESS LOCATION = 0X0F CHANNEL 2 ADDRESS LOCATION = 0X17 BIT 7BIT 6BIT 5 BIT 4BIT 3BIT 2BIT 1BIT 0 Unused SONET APS Recovery Time DisableCh_n JA RESET Ch_n JA1 Ch_n JA in Tx Path Ch_n JA0 Ch_n R/O R/O R/O R/WR/W R/WR/W R/W 00 0 00 001 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |