TDA8777HLSLASH33SLASHC1 datasheet(9/18 Pages) PHILIPS

9 / 18 page

TDA8777_3

Preliminary data sheet

Rev. 03 — 15 August 2005

9 of 18

Philips Semiconductors

TDA8777

Triple 10-bit video DAC, up to 330 MHz sample frequency

Timing

fCLK

clock frequency

TDA8777HL/14/C1

140

MHz

TDA8777HL/24/C1

240

MHz

TDA8777HL/33/C1

330

MHz

td(p)

pipeline delay

in clock cycles

2.5

tsu(i)

input setup time

see Figure 4

0.15

th(i)

input hold time

see Figure 4

--ns

td(o)

output delay time

see Figure 4

3.75

Table 6:

Characteristics …continued

Typical values measured at VDDA = 3.3 V; RRSET = 560 Ω; Tamb =25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Output delay (td(o)) is measured from the 50 % point of the rising edge of CLK to the 50 % point of full-scale transition.

Fig 4.

Timing diagram digital inputs and analog outputs

001aaa892

CLK

Analog outputs

(OUTB, OUTB,

OUTG, OUTG

OUTR, OUTR)

td(o)

Digital inputs

(R9 to R0, G9 to G0,

B9 to B0, SYNC,

BLANK)

th(i)

tsu(i)

DATA

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