Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

AM79C930 Datasheet(PDF) 86 Page - Advanced Micro Devices

Part # AM79C930
Description  PCnet-Mobile Single-Chip Wireless LAN Media Access Controller
PDF  161 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM79C930 Datasheet(HTML) 86 Page - Advanced Micro Devices

Back Button AM79C930 Datasheet HTML 82Page - Advanced Micro Devices AM79C930 Datasheet HTML 83Page - Advanced Micro Devices AM79C930 Datasheet HTML 84Page - Advanced Micro Devices AM79C930 Datasheet HTML 85Page - Advanced Micro Devices AM79C930 Datasheet HTML 86Page - Advanced Micro Devices AM79C930 Datasheet HTML 87Page - Advanced Micro Devices AM79C930 Datasheet HTML 88Page - Advanced Micro Devices AM79C930 Datasheet HTML 89Page - Advanced Micro Devices AM79C930 Datasheet HTML 90Page - Advanced Micro Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 86 / 161 page
background image
AMD
P R E L I M I N A R Y
86
Am79C930
Transceiver Attachment Interface
Registers (TIR Space)
The Transceiver Attachment Interface (TAI) Unit con-
tains a total of 64 registers. Thirty-two of the registers
are directly accessible from the 80188 embedded core
and from the system interface through the BIU. The
other 32 registers are indirectly accessed by first writing
an INDEX value into the TCR Index Register (TIR24)
and then executing a read or write operation to the TCR
Data Port (TIR25). Since the indirectly accessible regis-
ters are used mostly for TAI configuration purposes, this
set of registers is labeled TAI Configuration Registers
(TCR). The following section describes the directly ac-
cessible registers of the TAI, or TIR.
The set of 64 TAI registers is intended primarily for use
by the 80188 firmware. However, access through the
system interface bus to the TAI register set is provided
to allow for direct access by driver code for diagnostic
and other purposes.
The exact location of the TIR register set as viewed from
the system interface will depend upon the choice of
mapping scheme as indicated by the Expand I/O Win-
dow bit (bit 2 of the BSS register (SIR1)). The following
tables give the address for each of the directly accessi-
ble TIRs for each of the system interface modes for each
of the two mapping schemes, as well as the address for
each register as it appears in the memory map of the
80188 embedded core.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com