AM79C930 datasheet(107/161 Pages) AMD

107 / 161 page

P R E L I M I N A R Y

AMD

107

Am79C930

to delay the start of CRC8 and CRC32 and DC bias control

calculation for both receive and transmit frames. The physical

header field is assumed to begin after the Start of Frame Delimiter

has been detected.

TCR4: Antenna Diversity Timer

This register is the Antenna Diversity Timer register

used to control antenna dwell time during antenna

diversity measurements.

CONFIGURATION REGISTER INDEX:

04h

Bit

Name

Reset Value

Description

ANTEN

Antenna Diversity Enable. When set to a 1, the internal antenna di-

versity logic is used to select the antenna. When set to a 0, software

has control over antenna selection through the ANTS bit of

TIR26[4] and the ANTSLTLD bit of TCR7[1]. Dwell times for an-

tenna measurements are still used to obtain RSSI data when this bit

is set to 0, but final antenna selection will be controlled by software.

Reserved

–

Reserved. Must be written as a 0. Reads of this bit produce

undefined data.

5–0

ADT[5:0]

00h

Antenna Diversity Timer. Dwell time per antenna in time steps of

CLKIN period times 20 when the CLKGT20 bit of MIR9 is set to 0,

and time steps of CLKIN period times 40, when the CLKGT20 bit of

MIR9 is set to 1. When the value in this register is “00,” then the di-

versity switching function is disabled.

TCR5: TX Ramp Up Timing

This register is the TX Ramp Up Timing register. This

enable signals.

CONFIGURATION REGISTER INDEX:

05h

Bit

Name

Reset Value

Description

7:4

TGAP1[3:0]

Transmit Timing Gap 1. These bits are used to determine the gap

between the assertion of the

T1 signal and the assertion of the T2

signal.

T1 and T2 can be used to control the timing of the TXCMD

and

TXPE pins, respectively. The interval is programmable with a

resolution equal to 20 times the CLKIN period when the CLKGT20

bit of MIR9 is set to 0 and a resolution equal to 40 times the CLKIN

period when the CLKGT20 bit of MIR9 is set to 1. For a 1Mbs data

rate with CLKIN = 20MHz and CLKGT20 = 0, the resolution is 1

µ.

3:0

TGAP2[3:0]

Transmit Timing Gap 2. These bits are used to determine the gap

between the assertion of the

T2 signal and the assertion of the T3

signal. The interval is programmable with a resolution equal to 20

times the CLKIN period when the CLKGT20 bit of MIR9 is set to 0

and a resolution equal to 40 times the CLKIN period when the

CLKGT20 bit of MIR9 is set to 1. For a 1 Mbs data rate with CLKIN =

20 MHz and CLKGT20 = 0, the resolution is 1

µ.

AM79C930 Datasheet(PDF) 107 Page - Advanced Micro Devices

AM79C930 Datasheet(HTML) 107 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL