Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

Preview PDF HTML

MCP2517FD Datasheet(PDF) 29 Page - Microchip Technology

Part # MCP2517FD
Description  External CAN FD Controller with SPI Interface
PDF  98 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP2517FD Datasheet(HTML) 29 Page - Microchip Technology

Back Button MCP2517FD Datasheet HTML 25Page - Microchip Technology MCP2517FD Datasheet HTML 26Page - Microchip Technology MCP2517FD Datasheet HTML 27Page - Microchip Technology MCP2517FD Datasheet HTML 28Page - Microchip Technology MCP2517FD Datasheet HTML 29Page - Microchip Technology MCP2517FD Datasheet HTML 30Page - Microchip Technology MCP2517FD Datasheet HTML 31Page - Microchip Technology MCP2517FD Datasheet HTML 32Page - Microchip Technology MCP2517FD Datasheet HTML 33Page - Microchip Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 29 / 98 page
background image
 2017-2018 Microchip Technology Inc.
DS20005688B-page 29
MCP2517FD
REGISTER 3-9:
CiTDC – TRANSMITTER DELAY COMPENSATION REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—EDGFLTEN
SID11EN
bit 31
bit 24
U-0
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
—
—
—
—
—
—
TDCMOD<1:0>
bit 23
bit 16
U-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
—
TDCO<6:0>
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
TDCV<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-26
Unimplemented
: Read as ‘0’
bit 25
EDGFLTEN
: Enable Edge Filtering during Bus Integration state bit
1
= Edge Filtering enabled, according to ISO 11898-1:2015
0
= Edge Filtering disabled
bit 24
SID11EN
: Enable 12-Bit SID in CAN FD Base Format Messages bit
1
= RRS is used as SID11 in CAN FD base format messages: SID<11:0> = {SID<10:0>, SID11}
0
= Don’t use RRS; SID<10:0> according to ISO 11898-1:2015
bit 23-18
Unimplemented
: Read as ‘0’
bit 17-16
TDCMOD<1:0>
: Transmitter Delay Compensation Mode bits; Secondary Sample Point (SSP)
10-11 =
Auto; measure delay and add TDCO.
01
= Manual; Don’t measure, use TDCV + TDCO from register
00
= TDC Disabled
bit 15
Unimplemented
: Read as ‘0’
bit 14-8
TDCO<6:0>
: Transmitter Delay Compensation Offset bits; Secondary Sample Point (SSP)
Two’s complement; offset can be positive, zero, or negative.
011 1111
= 63 x TSYSCLK
...
000 0000
= 0 x TSYSCLK
...
111 1111
= –64 x TSYSCLK
bit 7-6
Unimplemented
: Read as ‘0’
bit 5-0
TDCV<5:0>
: Transmitter Delay Compensation Value bits; Secondary Sample Point (SSP)
11 1111
= 63 x TSYSCLK
...
00 0000 = 0 x TSYSCLK
Note 1:
This register can only be modified in Configuration mode.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com