ADSP-SC571KSWZ-4 datasheet(7/142 Pages) AD

7 / 142 page

Rev. B

Page 7 of 142

June 2018

ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573

L1 Memory

Figure 5 shows the ADSP-SC57x/ADSP-2157x memory map.

Each SHARC+ core has a tightly coupled L1 SRAM of up to

3 Mb. Each SHARC+ core can access code and data in a single

cycle from this memory space. The ARM Cortex-A5 core can

also access this memory space with multicycle accesses.

In the SHARC+ core private address space, both cores have L1

memory.

SHARC+ core memory-mapped register (CMMR) address

space is 0x00000000 through 0x0003FFFF in normal word

(32-bit). Each block can be configured for different combina-

tions of code and data storage. Of the 3 Mb SRAM, up to

1024 Kb/512 Kb can be configured for data memory (DM),

program memory (PM), and instruction cache. Each memory

block supports single-cycle, independent accesses by the core

processor and I/O processor. The memory architecture, in com-

bination with its separate on-chip buses, allows two data

transfers from the core and one from the direct memory access

(DMA) engine in a single cycle.

The SRAM of the processor can be configured as a maximum of

96k words of 32-bit data, 192k words of 16-bit data, 64k words

of 48-bit instructions (or 40-bit data), or combinations of differ-

ent word sizes up to 3 Mb. All of the memory can be accessed as

8-bit, 16-bit, 32-bit, 48-bit, or 64-bit words. Support of a 16-bit

floating-point storage format doubles the amount of data that

can be stored on chip.

Conversion between the 32-bit floating-point and 16-bit float-

ing-point formats is performed in a single instruction. While

each memory block can store combinations of code and data,

accesses are most efficient when one block stores data using the

DM bus for transfers, and the other block stores instructions

and data using the PM bus for transfers.

Using the DM and PM buses, with each bus dedicated to a

memory block, assures single-cycle execution with two data

transfers. In this case, the instruction must be available in the

cache.

Figure 4. SHARC+ SIMD Core Block Diagram

SIMD Core

11-STAGE

PROGRAM SEQUENCER

PM ADDRESS 32

PM DATA 64

DM DATA 64

DM ADDRESS 32

DAG1

16 × 32

MRF

80-BIT

ALU

MULTIPLIER

SHIFTER

PEx

DATA

16 × 40-BIT

DMD/PMD 64

ASTATx

STYKx

ASTATy

STYKy

PEy

DATA

16 × 40-BIT

MRB

80-BIT

MSB

80-BIT

MSF

80-BIT

DAG2

16 × 32

ALU

MULTIPLIER

SHIFTER

DATA

SWAP

SYSTEM

I/F

USTAT

PM ADDRESS 24

PM DATA 48

DEBUG

TRACE

FLAGS

CEC

BTB

CONFLICT

CACHE

IMIF

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