ADSP-SC571KSWZ-4 datasheet(8/142 Pages) AD

8 / 142 page

Rev. B

Page 8 of 142

June 2018

ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573

The system configuration is flexible, but a typical configuration

is 512 Kb DM, 128 Kb PM, and 128 Kb of instruction cache,

with the remaining L1 memory configured as SRAM. Each

addressable memory space outside the L1 memory can be

accessed either directly or via cache.

The memory map in Table 4 gives the L1 memory address space

and shows multiple L1 memory blocks offering a configurable

mix of SRAM and cache.

L1 Master and Slave Ports

Each SHARC+ core has two master ports and two slave ports to

and from the system fabric. One master port fetches instruc-

tions. The second master port drives data to the system world.

Slave port 1 together with slave port 2 (MDMA) run conflict

free access to the individual memory blocks. For the slave port

address, refer to the L1 memory address map in Table 4.

L1 On-Chip Memory Bandwidth

The internal memory architecture allows programs to have four

accesses at the same time to any of the four blocks, assuming no

block conflicts. The total bandwidth is realized using both the

DMD and PMD buses (2 × 64-bits CCLK speed and 2 × 32-bit

SYSCLK speed).

Instruction and Data Cache

The ADSP-SC57x/ADSP-2157x processors also include a

traditional instruction cache (I-cache) and two data caches

(D-cache) (PM/DM caches) with parity support for all caches.

These caches support one instruction access and two data

accesses over the DM and PM buses, per CCLK cycle. The cache

controllers automatically manage the configured L1 memory.

The system can configure part of the L1 memory for automatic

management by the cache controllers. The sizes of these caches

are independently configurable from 0 kB to a maximum of

128 kB each. The memory not managed by the cache controllers

is directly addressable by the processors. The controllers ensure

the data coherence between the two data caches. The caches

provide user-controllable features such as full and partial lock-

ing, range bound invalidation, and flushing.

System Event Controller (SEC) Input

The output of the system event controller (SEC) controller is

forwarded to the core event controller (CEC) to respond

directly to all unmasked system-based interrupts. The SEC also

supports nesting including various SEC interrupt channel arbi-

tration options. The processor automatically stacks the

arithmetic status (ASTATx and ASTATy) registers and mode

(MODE1) register in parallel with the interrupt servicing for all

SEC channels.

Core Memory-Mapped Registers (CMMR)

The core memory-mapped registers (CMMR) control the L1

instruction and data cache, BTB, L2 cache, parity error, system

control, debug, and monitor functions.

SHARC+ CORE ARCHITECTURE

The ADSP-SC57x/ADSP-2157x processors are code compatible

at the assembly level with the ADSP-2148x, ADSP-2147x,

ADSP-2146x, ADSP-2137x, ADSP-2136x, ADSP-2126x,

ADSP-2116x, and with the first-generation ADSP-2106x

SHARC processors.

The ADSP-SC57x/ADSP-2157x processors share architectural

features with the ADSP-2126x, ADSP-2136x, ADSP-2137x,

ADSP-214xx, and ADSP-2116x SIMD SHARC processors,

shown in Figure 4 and detailed in the following sections.

Figure 5. ADSP-SC57x/ADSP-2157x Memory Map

0x FFFF FFFF

0x C000 0000

0x 8000 0000

0x 6000 0000

0x 5000 0000

0x 4C00 0000

0x 4800 0000

0x 4400 0000

0x 4000 0000

0x 3000 0000

0x 28B8 FFFF

0x 28A4 0000

0x 2838 FFFF

0x 2824 0000

0x 202B FFFF

0x 201B FFFF

0x 2028 0000

0x 2011 7FFF

0x 2824 0000

0x 2018 0000

0x 2010 FFFF

0x 2010 8000

0x 2011 8000

0x 2011 0000

0x 2010 0000

DMC0 (1GB)

SPI2 FLASH (512MB)

SYSTEM MMR

RESERVED

SHARC2 L1 MULTI-MEMORY SPACE

RESERVED

SHARC1 L1 MULTI-MEMORY SPACE

RESERVED

L2 BOOT ROM 2 (0.25Mb)

(SHARC® CORES)

L2 SRAM (8Mb)

L2 BOOT ROM 0 (0.25Mb)

(ARM® CORE 0)

L2 BOOT ROM 1 (0.25Mb)

(SHARC® CORES)

0x 2000 0000

0x 0038 FFFF

0x 0038 0000

0x 0030 FFFF

0x 0030 0000

0x 002D FFFF

0x 002C 0000

0x 0025 FFFF

0x 0024 0000

0x 0000 0000

RESERVED

L1 BLOCK 3 SRAM (0.5Mb)

RESERVED

L1 BLOCK 2 SRAM (0.5Mb)

L1 BLOCK 1 SRAM (1Mb)

L1 BLOCK 0 SRAM (1Mb)

RESERVED/CORE MMRs/

OTHER MEMORY ALIASES

RESERVED

ARM® L2 CONFIG REGS (4KB)

RESERVED

ARM® BOOT (32KB)

0x 2000 0000

0x 1000 1000

0x 1000 0000

0x 0000 7FFF

0x 0000 0000

UNIFIED

BYTE ADDRESS

SPACE

RESERVED

0x 2010 8000

L2 BOOT ROM 1 (0.25Mb)

(SHARC® CORES)

L2 BOOT ROM 2 (0.25Mb)

(SHARC® CORES)

RESERVED

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