ADSP-SC571KSWZ-4 datasheet(91/142 Pages) AD

91 / 142 page

Rev. B

Page 91 of 142

June 2018

ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573

Asynchronous Sample Rate Converter (ASRC)—Serial Input Port

The ASRC input signals are routed from the DAI0_PINx pins using the SRU. Therefore, the timing specifications provided in Table 61 are

valid at the DAI0_PINx pins.

Table 61. ASRC, Serial Input Port

Parameter

Min

Max

Unit

Timing Requirements

tSRCSFS

1 The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. The input of

the PCG can be either CLKIN or any of the DAI pins.

Frame Sync Setup Before Serial Clock Rising Edge

tSRCHFS

Frame Sync Hold After Serial Clock Rising Edge

5.5

tSRCSD

Data Setup Before Serial Clock Rising Edge

tSRCHD

Data Hold After Serial Clock Rising Edge

5.5

tSRCCLKW

Clock Width

tSCLK0 – 1

tSRCCLK

Clock Period

2 × tSCLK0

Figure 34. ASRC Serial Input Port Timing

DAI0_PIN20–1

(SCLK)

SAMPLE EDGE

DAI0_PIN20–1

(FS)

DAI0_PIN20–1

(SDATA)

tSRCCLK

tSRCCLKW

tSRCSFS

tSRCHFS

tSRCHD

tSRCSD

ADSP-SC571KSWZ-4 Datasheet(PDF) 91 Page - Analog Devices

ADSP-SC571KSWZ-4 Datasheet(HTML) 91 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL