H8SLASH3002 datasheet(13/700 Pages) RENESAS

13 / 700 page

Section 14

A/D Converter............................................................................................ 479

14.1

Overview ........................................................................................................................ 479

14.1.1

Features........................................................................................................... 479

14.1.2

Block Diagram................................................................................................ 480

14.1.3

Input Pins ........................................................................................................ 481

14.1.4

14.2

Register Descriptions...................................................................................................... 483

14.2.1

A/D Data Registers A to D (ADDRA to ADDRD) ........................................ 483

14.2.2

A/D Control/Status Register (ADCSR) .......................................................... 484

14.2.3

A/D Control Register (ADCR) ....................................................................... 487

14.3

CPU Interface ................................................................................................................. 488

14.4

Operation ........................................................................................................................ 489

14.4.1

Single Mode (SCAN = 0) ............................................................................... 489

14.4.2

Scan Mode (SCAN = 1).................................................................................. 491

14.4.3

Input Sampling and A/D Conversion Time .................................................... 493

14.4.4

External Trigger Input Timing........................................................................ 494

14.5

Interrupts ........................................................................................................................ 495

14.6

Usage Notes .................................................................................................................... 495

Section 15

RAM ............................................................................................................. 501

15.1

Overview ........................................................................................................................ 501

15.1.1

Block Diagram................................................................................................ 501

15.1.2

15.2

System Control Register (SYSCR)................................................................................. 502

15.3

Operation ........................................................................................................................ 503

Section 16

Clock Pulse Generator............................................................................. 505

16.1

Overview ........................................................................................................................ 505

16.1.1

Block Diagram................................................................................................ 505

16.2

Oscillator Circuit ............................................................................................................ 506

16.2.1

Connecting a Crystal Resonator ..................................................................... 506

16.2.2

External Clock Input....................................................................................... 508

16.3

Duty Adjustment Circuit................................................................................................. 511

16.4

Prescalers ........................................................................................................................ 511

Section 17

Power-Down State .................................................................................... 513

17.1

Overview ........................................................................................................................ 513

17.2

Register Configuration.................................................................................................... 514

17.2.1

System Control Register (SYSCR)................................................................. 514

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