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ADSP21569WCBCZ10RL Datasheet(PDF) 36 Page - Analog Devices

Part # ADSP21569WCBCZ10RL
Description  SHARC Single Core High Performance DSP (Up to 1 GHz)
PDF  104 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP21569WCBCZ10RL Datasheet(HTML) 36 Page - Analog Devices

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Rev. B
|
Page 36 of 104
|
February 2021
ADSP-21562/21563/21565/21566/21567/21569
GPIO MULTIPLEXING FOR 120-LEAD LQFP PACKAGE
Table 16 and Table 17 identify the pin functions that are multi-
plexed on the general-purpose I/O pins of the 120-lead LQFP
package.
Table 16. Signal Multiplexing for Port A
Signal Name
Multiplexed Function 0
Multiplexed Function 1
Multiplexed Function 2
Multiplexed Function Input Tap
PA_00
SPI2_MISO
OSPI0_MISO/D1
PA_01
SPI2_MOSI
OSPI0_MOSI/D0
PA_02
SPI2_D2
OSPI0_D2
TWI3_SCL
TM0_ACLK3
PA_03
SPI2_D3
OSPI0_D3
TWI3_SDA
PA_04
SPI2_CLK
OSPI0_CLK
PA_05
SPI2_SEL1
OSPI0_SEL1
SPI2_SS
PA_06
SPI0_CLK
UART0_TX
OSPI0_D4
TM0_ACLK1
PA_07
SPI0_MISO
UART0_RX
OSPI0_D5
TM0_ACI0
PA_08
SPI0_MOSI
UART0_RTS
OSPI0_D6
TM0_ACLK2
PA_09
SPI0_SEL1
UART0_CTS
OSPI0_D7
SPI0_SS
PA_10
TWI0_SCL
SPI1_CLK
TM0_TMR0
PA_11
TWI0_SDA
SPI1_MISO
HADC0_EOC_DOUT
TM0_ACI4
PA_12
C0_FLG0
SPI1_MOSI
TM0_TMR1
PA_13
C0_FLG1
SPI1_SEL1
TM0_TMR2
SPI1_SS
PA_14
TWI2_SCL
SPI1_D2
UART1_RX
TM0_ACI1
PA_15
TWI2_SDA
SPI1_D3
UART1_TX
Table 17. Signal Multiplexing for Port B
Signal Name
Multiplexed Function 0
Multiplexed Function 1
Multiplexed Function 2
Multiplexed Function Input Tap
PB_00
MLB0_DAT
TWI1_SCL
UART1_RTS
TM0_ACI3
PB_01
MLB0_SIG
TWI1_SDA
UART1_CTS
TM0_CLK
PB_02
MLB0_CLK
C0_FLG3
TM0_ACLK4
PB_03
TM0_TMR3
C0_FLG2
SPI2_SEL2
CNT0_UD
PB_04
TM0_TMR4
SPI1_RDY
CNT0_ZM
PB_05
TM0_TMR5
SPI2_RDY
SPI0_SEL2
CNT0_DG



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