ADSP21569WCBCZ10RL datasheet(13/104 Pages) AD

13 / 104 page

Rev. B

Page 13 of 104

February 2021

ADSP-21562/21563/21565/21566/21567/21569

System Protection Unit (SPU)

The system protection unit (SPU) guards against accidental or

unwanted access to an MMR space of the peripheral by provid-

ing a write protection mechanism. The user can choose and

configure the protected peripherals as well as configure which of

the three system MMR masters (SHARC+ core, memory DMA,

and Arm

® CoreSightTM debug) the peripherals are guarded

against.

The SPU is also part of the security infrastructure. Along with

providing write protection functionality, the SPU is employed

to define which resources in the system are secure or nonsecure

as well as block access to secure resources from nonsecure

masters.

System Memory Protection Unit (SMPU)

The system memory protection unit (SMPU) provides memory

protection against read and/or write transactions to defined

regions of memory. There are SMPU units in the ADSP-2156x

processors for each memory space, except for SHARC L1

memory.

The SMPU is also part of the security infrastructure. It allows

the user to protect against arbitrary read and/or write transac-

tions and allows regions of memory to be defined as secure and

prevent nonsecure masters from accessing those memory

regions.

SECURITY FEATURES DISCLAIMER

Analog Devices does not guarantee that the Security Features

described herein provide absolute security. ACCORDINGLY,

ANALOG DEVICES HEREBY DISCLAIMS ANY AND ALL

EXPRESS AND IMPLIED WARRANTIES THAT THE

SECURITY FEATURES CANNOT BE BREACHED,

COMPROMISED, OR OTHERWISE CIRCUMVENTED AND

IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR

ANY LOSS, DAMAGE, DESTRUCTION, OR RELEASE OF

DATA, INFORMATION, PHYSICAL PROPERTY, OR

INTELLECTUAL PROPERTY.

SAFETY FEATURES

The ADSP-2156x processors are designed to support functional

safety applications. Whereas the level of safety is mainly domi-

nated by the system concept, the following primitives are

provided by the processors to build a robust safety concept.

Multiparity Bit Protected SHARC+ Core L1 Memories

In the SHARC+ core L1 memory space, whether SRAM or

cache, multiple parity bits protect each word to detect the single

event upsets that occur in all RAMs. Parity also protects the

cache tags and BTB.

Error Correcting Code (ECC) Protected L2 Memories

Error correcting code (ECC) corrects single event upsets. A sin-

gle error correct/double error detect (SEC/DED) code protects

the L2 memory. By default, ECC is enabled, but it can be dis-

abled on a per bank basis. Single-bit errors correct

transparently. If enabled, dual-bit errors can issue a system

event or fault. ECC protection is fully transparent to the user,

even if L2 memory is read or written by 8-bit or 16-bit entities.

Parity Protected Peripheral Memories

Parity protection is added to the following peripheral memories:

•ASRC

• IIR

•FIR

•CRYPTO

•MLB

•TRACE

Cyclic Redundancy Check (CRC) Protected Memories

Whereas parity bit and ECC protection mainly protect against

random soft errors in L1 and L2 memory cells, the CRC engines

can protect against systematic errors (pointer errors) and static

content (instruction code) of L1, L2, and even L3 memories

(DDR3, DDR3L). The processors feature two CRC engines that

are embedded in the memory to memory DMA controllers.

CRC checksums can be calculated or compared automatically

during memory transfers. Alternatively, single or multiple

memory regions can be continuously scrubbed by a single DMA

work unit as per DMA descriptor chain instructions. The CRC

engine also protects data loaded during the boot process.

Signal Watchdogs

The 10 general-purpose timers feature modes to monitor off-

chip signals. The watchdog period mode monitors whether

external signals toggle with a period within an expected range.

The watchdog width mode monitors whether the pulse widths

of external signals are within an expected range. Both modes

help detect undesired toggling or lack of toggling of system level

signals.

System Event Controller (SEC)

Besides system events, the system event controller (SEC) further

supports fault management, including fault action configura-

tion as timeout, internal indication by system interrupt, or

external indication through the SYS_FAULT pin and system

reset.

Memory Error Controller (MEC)

The memory error controller (MEC) manages memory par-

ity/ECC errors and warnings from the cores and peripherals

and sends out interrupts and triggers.

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