LTC2430IGN datasheet(14/40 Pages) LINER

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LTC2430/LTC2431

24301f

+FS, the conversion result is clamped to the value corre-

sponding to the +FS + 1LSB. For differential input voltages

below –FS, the conversion result is clamped to the value

corresponding to –FS – 1LSB.

Frequency Rejection Selection (FO)

The LTC2430/LTC2431 internal oscillator provides better

than 110dB normal mode rejection at the line frequency

and all its harmonics for 50Hz

±2% or 60Hz ±2%. For

60Hz rejection, FO should be connected to GND while for

50Hz rejection the FO pin should be connected to VCC.

The selection of 50Hz or 60Hz rejection can also be made

by driving FO to an appropriate logic level. A selection

change during the sleep or data output states will not

disturb the converter operation. If the selection is made

during the conversion state, the result of the conversion in

progress may be outside specifications but the following

conversions will not be affected.

When a fundamental rejection frequency different from

50Hz or 60Hz is required or when the converter must be

synchronized with an outside source, the LTC2430 or

LTC2431 can operate with an external conversion clock.

The converter automatically detects the presence of an

external clock signal at the FO pin and turns off the internal

oscillator. The frequency fEOSC of the external signal must

be at least 5kHz to be detected. The external clock signal

duty cycle is not significant as long as the minimum and

maximum specifications for the high and low periods tHEO

and tLEO are observed.

While operating with an external conversion clock of a

frequency fEOSC, the LTC2430 or LTC2431 provides better

than 110dB normal mode rejection in a frequency range

fEOSC/2560 ±4% and its harmonics. The normal mode

rejection as a function of the input frequency deviation

from fEOSC/2560 is shown in Figure 4.

Whenever an external clock is not present at the FO pin, the

converter (LTC2430 or LTC2431) automatically activates

its internal oscillator and enters the Internal Conversion

Clock mode. Its operation will not be disturbed if the

change of conversion clock source occurs during the

sleep state or during the data output state while the con-

verter uses an external serial clock. If the change occurs

during the conversion state, the result of the conversion in

progress may be outside specifications but the following

conversions will not be affected. If the change occurs

during the data output state and the converter is in the

Internal SCK mode, the serial clock duty cycle may be

affected but the serial data stream will remain valid.

Table 3 summarizes the duration of each state and the

achievable output data rate as a function of FO.

SERIAL INTERFACE PINS

The LTC2430/LTC2431 transmit the conversion results

and receives the start of conversion command through a

synchronous 3-wire interface. During the conversion and

sleep states, this interface can be used to assess the

converter status and during the data output state it is used

to read the conversion result.

Serial Clock Input/Output (SCK)

The serial clock signal present on SCK is used to synchro-

nize the data transfer. Each bit of data is shifted out the

SDO pin on the falling edge of the serial clock.

In the Internal SCK mode of operation, the SCK pin is an

output and the converter (LTC2430 or LTC2431) creates

its own serial clock by dividing the internal conversion clock

by 8. In the External SCK mode of operation, the SCK pin

is used as input. The internal or external SCK mode is

selected on power-up and then reselected every time a

HIGH-to-LOW transition is detected at the CS pin. If SCK

Figure 4. LTC2430/LTC2431 Normal Mode Rejection When

Using an External Oscillator of Frequency fEOSC

APPLICATIO S I FOR ATIO

DIFFERENTIAL INPUT SIGNAL FREQUENCY

DEVIATION FROM NOTCH FREQUENCY fEOSC/2560(%)

–12

–8

–4

048

2431 F04

–80

–85

–90

–95

–100

–105

–110

–115

–120

–125

–130

–135

–140

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