LTC2430IGN datasheet(24/40 Pages) LINER

24 / 40 page

LTC2430/LTC2431

24301f

The typical +FS and –FS errors as a function of the sum of

the source resistance seen by IN+ and IN– for large values

of CIN are shown in Figure 15.

In addition to this gain error, an offset error term may also

appear. The offset error is proportional with the mismatch

between the source impedance driving the two input pins

IN+ and IN– and with the difference between the input and

reference common mode voltages. While the input drive

circuit nonzero source impedance combined with the

converter average input current will not degrade the INL

performance, indirect distortion may result from the modu-

lation of the offset error by the common mode component

of the input signal. Thus, when using large CIN capacitor

values, it is advisable to carefully match the source imped-

ance seen by the IN+ and IN– pins. When FO = LOW

(internal oscillator and 60Hz notch), every 1

Ω mismatch

in source impedance transforms a full-scale common

mode input signal into a differential mode input signal of

0.023ppm. When FO = HIGH (internal oscillator and 50Hz

notch), every 1

Ω mismatch in source impedance trans-

forms a full-scale common mode input signal into a

differential mode input signal of 0.019ppm. When FO is

driven by an external oscillator with a frequency fEOSC,

every 1

Ω mismatch in source impedance transforms a

full-scale common mode input signal into a differential

mode input signal of 0.15 • 10–6 • fEOSCppm. Figure 16

shows the typical offset error due to input common mode

voltage for various values of source resistance imbalance

between the IN+ and IN– pins when large CIN values are

used.

If possible, it is desirable to operate with the input signal

common mode voltage very close to the reference signal

common mode voltage as is the case in the ratiometric

measurement of a symmetric bridge. This configuration

eliminates the offset error caused by mismatched source

impedances.

The magnitude of the dynamic input current depends upon

the size of the very stable internal sampling capacitors and

upon the accuracy of the converter sampling clock. The

accuracy of the internal clock over the entire temperature

and power supply range is typically better than 1%. Such

APPLICATIO S I FOR ATIO

Figure 15a. + FS Error vs RSOURCE at IN+ or IN– (Large CIN)

Figure 15b. – FS Error vs RSOURCE at IN

+ or IN– (Large CIN)

RSOURCE (Ω)

800

2431 F15a

200

400 500

1000

600

100

300

900

700

CIN = 0.01µF

CIN = 0.1µF

CIN = 1µF, 10µF

VCC = 5V

VREF+ = 5V

VREF– = GND

VIN+ = 3.75V

VIN– = 1.25V

FO = GND

TA = 25°C

RSOURCE (Ω)

–10

–5

800

2431 F15b

–15

–20

200

400 500

1000

600

100

300

900

700

CIN = 0.01µF

CIN = 0.1µF

CIN = 1µF, 10µF

VCC = 5V

VREF+ = 5V

VREF– = GND

VIN+ = 1.25V

VIN– = 3.75V

FO = GND

TA = 25°C

Figure 16. Offset Error vs Common Mode Voltage

(VINCM = VIN+ = VIN–) and Input Source Resistance Imbalance

(

∆RIN = RSOURCEIN+ – RSOURCEIN–) for Large CIN Values (CIN ≥ 1µF)

VINCM (V)

–20

–40

2.5

0.5

1.5

4.5

3.5

VCC = 5V

VREF+ = 5V

VREF– = GND

VIN+ = VIN– = VINCM

FO = GND

RSOURCEIN– = 500Ω

CIN = 10µF

TA = 25°C

2431 F16

∆RIN = +1k

∆RIN = +500Ω

∆RIN = +200Ω

∆RIN = 0Ω

∆RIN = –200Ω

∆RIN = –500Ω

∆RIN = –1k

LTC2430IGN Datasheet(PDF) 24 Page - Linear Technology

LTC2430IGN Datasheet(HTML) 24 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL