LTC2430IGN datasheet(22/40 Pages) LINER

22 / 40 page

LTC2430/LTC2431

24301f

between the FO signal trace and the input/reference sig-

nals. When the FO signal is parallel terminated near the

converter, substantial AC current is flowing in the loop

formed by the FO connection trace, the termination and the

ground return path. Thus, perturbation signals may be

inductively coupled into the converter input and/or refer-

ence. In this situation, the user must reduce to a minimum

the loop area for the FO signal as well as the loop area for

the differential input and reference connections.

Driving the Input and Reference

The input and reference pins of the converter (LTC2430 or

LTC2431) are directly connected to a network of sampling

capacitors. Depending upon the relation between the dif-

ferential input voltage and the differential reference volt-

age, these capacitors are switching between these four

pins transfering small amounts of charge in the process.

A simplified equivalent circuit is shown in Figure 11.

For a simple approximation, the source impedance RS

driving an analog input pin (IN+, IN–, REF+ or REF–) can be

considered to form, together with RSW and CEQ (see

Figure 11), a first order passive network with a time

constant

τ = (RS + RSW) • CEQ. The converter is able to

sample the input signal with better than 1ppm accuracy if

the sampling period is at least 14 times greater than the

input circuit time constant

τ. The sampling process on the

four input analog pins is quasi-independent so each time

constant should be considered by itself and, under worst-

case circumstances, the errors may add.

When using the internal oscillator (FO = LOW or HIGH), the

LTC2430/LTC2431’s front-end switched-capacitor net-

work is clocked at 76800Hz corresponding to a 13

µs

sampling period. Thus, for settling errors of less than

1ppm, the driving source impedance should be chosen

such that

τ ≤13µs/14 = 920ns. When an external oscillator

of frequency fEOSC is used, the sampling period is 2/fEOSC

and, for a settling error of less than 1ppm,

τ ≤ 0.14/fEOSC.

Input Current

If complete settling occurs on the input, conversion re-

sults will be unaffected by the dynamic input current. An

incomplete settling of the input signal sampling process

may result in gain and offset errors, but it will not degrade

the INL performance of the converter. Figure 11 shows the

mathematical expressions for the average bias currents

flowing through the IN+ and IN– pins as a result of the

APPLICATIO S I FOR ATIO

Figure 11. LTC2430/LTC2431 Equivalent Analog Input Circuit

VREF+

VIN+

VCC

RSW (TYP)

20k

ILEAK

VCC

ILEAK

VCC

RSW (TYP)

20k

CEQ

6pF

(TYP)

RSW (TYP)

20k

ILEAK

IIN+

VIN–

IIN–

IREF+

IREF–

2431 F11

ILEAK

VCC

ILEAK

SWITCHING FREQUENCY

fSW = 76800Hz INTERNAL OSCILLATOR (FO = LOW OR HIGH)

fSW = 0.5 • fEOSC EXTERNAL OSCILLATOR

VREF–

RSW (TYP)

20k

IIN

IREF

I REF

WHERE

AVG

INCM

REFCM

AVG

INCM

REFCM

AVG

REF

INCM

REFCM

REF

AVG

REF

INCM

REFCM

REF

−

() = +−

•

() = −+ −

•

() = •− +

•

−

•

() = −• − +

•

REF

VIN

INTERNAL OSCILLATOR

Hz Notch F

LOW

INTERNAL OSCILLATOR

Hz Notch F

HIGH

EXTERNAL OSCILLATOR

REF

REFCM

INCM

EOSC

=−













=−

−













()

=•

()

+−

43 2

52 0

666 1012

Ω

LTC2430IGN Datasheet(PDF) 22 Page - Linear Technology

LTC2430IGN Datasheet(HTML) 22 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL