LTC2430IGN datasheet(17/40 Pages) LINER

17 / 40 page

LTC2430/LTC2431

24301f

EOC = 0 once the conversion ends. On the falling edge of

EOC, the conversion result is loaded into an internal static

shift register. Data is shifted out the SDO pin on each

falling edge of SCK enabling external circuitry to latch data

on the rising edge of SCK. EOC can be latched on the first

rising edge of SCK. On the 24th falling edge of SCK, SDO

goes HIGH (EOC = 1) indicating a new conversion has

begun.

Internal Serial Clock, Single Cycle Operation

This timing mode uses an internal serial clock to shift out

the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 8.

In order to select the internal serial clock timing mode, the

serial clock pin (SCK) must be floating (Hi-Z) or pulled

HIGH prior to the falling edge of CS. The device will not

enter the internal serial clock mode if SCK is driven LOW

on the falling edge of CS. An internal weak pull-up resistor

is active on the SCK pin during the falling edge of CS;

therefore, the internal serial clock timing mode is auto-

matically selected if SCK is not externally driven.

Figure 6. External Serial Clock, Reduced Data Output Length

APPLICATIO S I FOR ATIO

SDO

SCK

(EXTERNAL)

DATA

OUTPUT

CONVERSION

SLEEP

TEST EOC

(OPTIONAL)

TEST EOC

DATA OUTPUT

Hi-Z

CONVERSION

2431 F06

MSB

SIG

BIT 8

BIT 19

BIT 9

BIT 20

BIT 21

BIT 22

EOC

BIT 23

BIT 0

EOC

Hi-Z

TEST EOC

VCC

REF+

REF–

SCK

IN+

IN–

SDO

GND

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG INPUT RANGE

–0.5VREF TO 0.5VREF

3-WIRE

SPI INTERFACE

µF

2.7V TO 5.5V

LTC2430/

LTC2431

= 50Hz REJECTION

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

VCC

the device aborts the data output state and immediately

initiates a new conversion. This is useful for systems not

requiring all 24 bits of output data, aborting an invalid con-

version cycle or synchronizing the start of a conversion.

External Serial Clock, 2-Wire I/O

This timing mode utilizes a 2-wire serial I/O interface. The

conversion result is shifted out of the device by an exter-

nally generated serial clock (SCK) signal, see Figure 7. CS

may be permanently tied to ground, simplifying the user

interface or isolation barrier.

The external serial clock mode is selected at the end of the

power-on reset (POR) cycle. The POR cycle is concluded

approximately 1ms after VCC exceeds 2V. The level applied

to SCK at this time determines if SCK is internal or external.

SCK must be driven LOW prior to the end of POR in order

to enter the external serial clock timing mode.

Since CS is tied LOW, the end-of-conversion (EOC) can be

continuously monitored at the SDO pin during the convert

and sleep states. EOC may be used as an interrupt to an

external controller indicating the conversion result is

ready. EOC = 1 while the conversion is in progress and

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