AT25XE321D datasheet(39/124 Pages) DIALOG

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Datasheet

2021-Aug-2

DS-AT25XE321D-160

Revision J

AT25XE321D

Datasheet

32-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory

with Multi-I/O Support

after the 8th clock (most significant bit of the command is transferred), hardware performs the operation. If the CS pin is raised

after the 9th or 10th clock (not a byte boundary), the operation is ignored and no ABh command is executed.

Similarly, if the ABh command fetches the device ID. Once the CS pin is asserted, 40 clock cycles are required: 8 clocks for the

command, 24 dummy clocks, and 8 clocks to shift out the device ID. If the CS pin is raised after the 40th clock, hardware transfers

the ID information, exits power-down mode, and completes the operation. However, if the CS pin is raised on the 41st of 42nd

clock (not a byte boundary), the ID information is still returned as that occurred in clocks 32 - 40, but the device does not exit

power-down mode.

4.14 ACTIVE STATUS INTERRUPT

When a program or erase operation is in progress, there are two ways to determine when the operation has finished.



Repeatedly poll bit 0 (RDY/BSY) of Status register 1 looking for a high to low transition.



Once the program or erase operation begins, execute the Active Status Interrupt (25h) command, and watch for a high to

low transition on the SO pin.

For example, assume a Byte/Page Program (02h) operation is initiated and 256 bytes are transferred into the buffer. Once the

CS pin is deasserted, indicating the completion of the 02h command, hardware sets the RDY/BSY bit and starts moving the data

to memory. Executing the 25h command causes hardware to drive the state of the RDY/BSY bit onto the SO pin. This allows

external logic to monitor the state of the SO pin for a high to low transition.

When the Active Status Interrupt (25h) command is used, the SO pin can be connected to an external interrupt controller. The

controller recognizes the high to low transition and takes the appropriate action. This command is an alternative to the polling of

the RDY/BSY bit in Status register 1 and uses less overhead than continually executing the 05h command to read the contents

of Status register 1.

4.15 LOW BATTERY DETECT

The AT25XE321D device includes a Low Battery Detect (EFh) command that can be used to probe the battery and determine its

status. The low battery detect function is programmable. Software uses Status register (SR6) to program parameters such as

what voltage level constitutes a low battery, and how much load is applied to the battery to determine the amount of charge left.

Another field sets the amount of time the desired load is applied to the battery.

Status register 6 is used in the following manner to determine the low battery status. For the exact programmable values for these

registers fields, see Section 5.4, Status Register 2.

Program the LBVL field (bits 5:3) of SR6 to set the low battery detect level. When a test is performed, the device does not

indicate a low voltage level until that level falls below the value programmed into this field. Values range from 1.8V to

3.2V in 200 mV increments.

Program the LBLD field (bits 2:1) of SR6 to indicate the amount of load applied to the battery for testing purposes. The

amount of load applied ranges from 0

μA to 10 mA.

Program the LBD field (bit 0) to indicate the amount of time the load selected by the LBLD field is applied to the battery.

Values of 100

μs and 1 ms are supported.

Execute the Low Battery Detect (EFh) command. This operation sets bits 7:6 (LBST) of SR6 to a value of 2’b01,

indicating that a low battery detect operation is in progress.

Software can poll bits 7:6 of SR6 to determine whether the test has completed. As long as the value of these bits is 2’b01

the battery test is in progress. Alternatively, the active status interrupt (25h) command can be used to determine when the

test has completed. See the previous subsection for more information on the active status interrupt command.

Once the operation is complete, bits 7:6 of SR6 indicate the result of the test. If the field contains a value of 2’b10, the

voltage of the battery is greater than the threshold set by the LBVL field. A value of 2’b11 indicates the voltage of the

battery is less than the threshold set by the LBVL field.

Bits 7:6 of SR6 can be reset by hardware when certain internal conditions are met. The user can reset this field by executing a

Terminate command (F0h). See Section 6.43, Low Battery Detect (EFh) for more information.

AT25XE321D Datasheet(PDF) 39 Page - Dialog Semiconductor

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