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Datasheet

2021-Aug-2

DS-AT25XE321D-160

Revision J

AT25XE321D

Datasheet

32-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory

with Multi-I/O Support

Table 1: Pin Descriptions

Symbol

Name and Function

Asserted

State

Type

CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is

deasserted, the device is be deselected and normally be placed in standby mode

(not Deep Power-Down mode), and the SO pin is in a high-impedance state. When

the device is deselected, data are not accepted on the SI pin.

A high-to-low transition on the CS pin is required to start an operation, and a low-

to-high transition is required to end an operation. When ending an internally self-

timed operation such as a program or erase cycle, the device does not enter the

standby mode until the completion of the operation.

Low

Input

SCK

SERIAL CLOCK: This pin provides a clock to the device and controls the flow of

data to and from the device. Command, address, and input data present on the

SI pin is always latched in on the rising edge of SCK, while output data on the SO

pin is always clocked out on the falling edge of SCK.

Input

SI (I/O0)

SERIAL INPUT: The SI pin shifts data into the device. The SI pin is used for all

data input including command and address sequences. Data on the SI pin is

always latched in on the rising edge of SCK.

With the Multi I/O Read commands, the SI pin becomes an output pin (I/O0) in

conjunction with other pins to allow either two or four bits of data on (I/O1:0 or

I/O3:0) to be clocked out on every falling edge of SCK.

Data present on the SI pin is ignored whenever the device is deselected (CS is

deasserted and the device is in the reset condition).

Input/

Output

SO (I/O1)

SERIAL OUTPUT: The SO pin shifts data out from the device. Data on the SO pin

is always clocked out on the falling edge of SCK.

With the Multi I/O Read commands, the SO pin remains an output pin (I/O1) in

conjunction with other pins to allow either two or four bits of data on (I/O1:0 or

I/O3:0) to be clocked out on every falling edge of SCK.

The SO pin is in a high-impedance state whenever the device is deselected (CS

is deasserted and the device is in the reset condition).

Input/

Output

WP (I/O2)

WRITE PROTECT: The WP pin controls the hardware locking feature of the de-

vice. When set, this bit prevents the Status Register from being written. This bit is

used in conjunction with other Status Register bits (CMPRT, BPSIZE, TB, and

BP[2:0]) to provide hardware protection of the memory array.

The WP pin is internally pulled-high and can be left floating if hardware controlled

protection is not used. However, it is recommended that the WP pin also be ex-

ternally connected to VCC whenever possible.

When the QE bit in Status Register 2 is set, enabling quad mode (Output or I/O),

the WP pin becomes bidirectional and functions as the IO2 pin used to transmit

address and/or data, depending on the transfer mode.

Low

Input/

Output

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