AT25XE321D datasheet(97/124 Pages) DIALOG

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Datasheet

2021-Aug-2

DS-AT25XE321D-160

Revision J

AT25XE321D

Datasheet

32-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory

with Multi-I/O Support



For this operation, the CS pin continues to be asserted after the 8th clock. In this operation, the CS pin is held low for the

time it takes to transfer the device ID. Therefore, 40 clocks are required to complete this operation; 8 for the command, 24

for the dummy bytes, and 8 clocks for the device ID.



The device ID is shifted out on the SO pin, with the most significant bit of the value being transmitted first. The device ID is

read out continuously until the CS pin is deasserted.

6.34.6 Transfer Sequence — Resume from Ultra-Deep Power-Down

To perform the resume from Ultra-Deep Power-Down operation, the CS pin is asserted and the information transferred as follows:



The ABh command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of

the command is transferred first.



Once CS is deasserted, hardware initiates an internal reset of the device and the SRAM contents are lost.



The device exits the Ultra-Deep Power-Down mode within the time tRUDPD defined in Section 7.5.

Figure 27 shows a timing diagram of this timing parameter.

Figure 27: Resume from Deep Power-Down or Ultra-Deep Power-Down

6.34.7 Programming Restrictions

The Resume from Deep Power-Down command adheres to the following programming restrictions.



The complete command must be clocked into the device before the CS pin is deasserted.



The CS pin must be deasserted on a byte boundary (multiple of eight bits). Otherwise, the device aborts the operation and

no action is taken.

SCK

MSB

ICC

10101011

OPCODE

HIGH-IMPEDANCE

Deep Power-Down Mode Current

Active Current

Standby Mode Current

RDPD

tRUDPD

Deep Power-Down mode or

Ultra-Deep Power-Down mode current

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