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AT25XE321D Datasheet(PDF) 76 Page - Dialog Semiconductor

Part # AT25XE321D
Description  32-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory with Multi-I/O Support
PDF  124 Pages
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Manufacturer  DIALOG [Dialog Semiconductor]
Direct Link  http://www.dialog-semiconductor.com/
Logo DIALOG - Dialog Semiconductor

AT25XE321D Datasheet(HTML) 76 Page - Dialog Semiconductor

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Datasheet
2021-Aug-2
DS-AT25XE321D-160
Revision J
76
© 2021 Dialog Semiconductor
AT25XE321D
Datasheet
32-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
6.16 BUFFER WRITE (84H)
Utilizing the Buffer Write command allows data to be written directly into the internal buffer without starting a write to the Flash
array at the same time. This write operation is typically used to write small amounts of data at a time to the buffer.
To prevent buffer data loss, do not perform a program or erase operation until the written data is being used, either through the
Buffer Read command or Buffer to Main Memory Program without Erase command.
6.16.1 Command Prerequisites
The Write Enable command (06h) must have been previously issued to the device to set the Write Enable Latch (WEL) bit in
Status Register 1.
6.16.2 Transfer Format
The 84h command follows the 1-1-1 transfer format described in Section 4.2, where the command, address, and data are
transferred on the SI pin. Figure 9 shows a buffer write operation with a one byte transfer. Additional data bytes can be transferred
as long as the CS pin remains low. Note that CS can only be deasserted on a byte boundary.
6.16.3 Transfer Sequence
To perform the Buffer Write operation, the CS pin is asserted and the information transferred as follows:
The 84 command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of
the command is transferred first.
Three address bytes are clocked in to specify the starting address location of the first byte to written within the buffer. A total
of 24 clocks are required to transfer the address. The most significant bit of the address (A[23]) is transferred first. Since the
buffer is only 256 bytes in size, the upper 16 bits of address (A[23:8]) are don’t care for this operation. Only the lower byte
(A[7:0]) is valid and selects one of the 256 buffer entries.
Data is input on the SI pin. Each byte transfer requires eight clock cycles. The data is always input with the most significant
bit of the byte transferred first. The number of bytes transferred is determined by software. The transfer can be anywhere
from a single byte to the entire 256 byte buffer.
After the last address byte has been clocked into the device, data can then be clocked in on subsequent clock cycles. If the
end of the buffer is reached, the device wraps around back to the beginning of the buffer. Data continues to be loaded into
the buffer until a low-to-high transition is detected on the CS pin.
6.16.4 Writing Buffer Entries
Hardware does not clear the buffer entries automatically prior to starting a Buffer Write command. This allows multiple Buffer Write
commands to be performed to update different parts of the buffer before writing the buffer to the Flash memory, or to update the
same buffer locations multiple times before writing to Flash memory. Buffer locations which are not updated can contain whatever
data is left in the buffer from the previous write operation.
6.16.5 Writing the Buffer Entries to Flash Memory
Once the Buffer Write operation is completed, the Buffer to Main Memory Page Program without Built-In Erase (88h) command
writes the full 256-byte page, even if less than 256 bytes were written to the buffer. For more information, see Section 6.17, Buffer
to Main Memory Page Program without Erase (88h).
6.16.6 Programming Restrictions
The Buffer Write command adheres to the following programming restrictions.
The CS pin must be deasserted on a byte boundary (multiple of eight bits). Otherwise, the device aborts the operation and
no action is taken.



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