AT25XE321D datasheet(20/124 Pages) DIALOG

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Datasheet

2021-Aug-2

DS-AT25XE321D-160

Revision J

AT25XE321D

Datasheet

32-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory

with Multi-I/O Support

A Dual Output (1-1-2) write operation is shown in Figure 11. An example of this operation is a Dual Output Byte/Page Program

(A2h).

Figure 11: Dual Output Write — 1-pin Command, 1-Pin Address, and 2-Pin Data

4.4 QUAD OUTPUT OPERATION (1-1-4)

The AT25XE321D supports the Quad Output mode which enhances overall throughput over the standard SPI and dual operation

modes by increasing the data transfer rate. In this mode, data is transferred on four pins; SI, SO, WP, and HOLD. This means

that only 1/4th the number of clocks are required to transfer the data relative to standard SPI mode. This is known as a 1-1-4

transfer which is defined as follows:



1-pin command, 1-pin address, and 4-pin data (1-1-4)

In Quad Output mode the command (C) and address (A) are driven to the memory device on the SI (IO0) pin. During write

operations, the SI (IO0), SO (IO1), WP (IO2), and HOLD (IO3) pins switched to inputs and the data is driven on all four pins,

allowing four data bits to be transferred on every clock. During read operations, once the command and address are transferred

on the SI (IO0) pin, the SI (IO0), SO (IO1), WP (IO2), and HOLD (IO3) pins switched to outputs and the data is driven on all four

pins, allowing four data bits to be transferred on every clock.

A 1-1-4 Quad Output read operation is shown in Figure 12. An example of this operation is a Quad Output Read (6Bh). Note that

this type of transfer can contain one or more dummy bytes between the end of the address and the beginning of the data output

depending on the type of command and the operating frequency. See Table 20 for more information.

Figure 12: Quad Output Transfer — 1-Pin Command, 1-Pin Address, and 4-Pin Data — Read Operation

6&.

6,6,2

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&&&&&&&&

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+,*+,03('$1&(

06%

'$7$ ,1

I/O0

(SI)

SCK

37 38

31 32

246

COMMAND

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AAA

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Address Bits A23-A0

DUMMY

DATA

OUT 1

DATA

OUT 2

DATA

OUT 3

DATA

OUT 4

DATA

OUT 5

I/O1

(SO)

High-Impedance

D5 D1 D5 D1 D5 D1 D5 D1 D5 D1

I/O2

(WP)

High-Impedance

D6 D2 D6 D2 D6 D2 D6 D2 D6 D2

I/O3

(HOLD)

MSB

High-Impedance

D7 D3 D7 D3 D7 D3 D7 D3 D7 D3

D4 D0 D4 D0 D4 D0 D4 D0 D4 D0

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