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ZLR64400ROMMCU Datasheet(PDF) 84 Page - Zilog, Inc. |
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ZLR64400ROMMCU Datasheet(HTML) 84 Page - Zilog, Inc. |
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84 / 155 page ![]() PS024502-1205 P R E L I M I N A R Y Counter/Timer Registers ZLR64400 ROM MCU Product Specification 74 Counter/Timer 8 Control Register The Counter/Timer 8 Control Register controls the timer function of the T8 timer. This Bank D register is described in Table 35. Writing a 1 to CTR0[5] is the only way to reset the Terminal Count status condition. Re- set this bit before using/enabling the counter/timers. Be careful when using the OR or AND commands to manipulate CTR0, bit 5 and CTR1, bits 0 and 1 (Demodulation Mode). These instructions use a Read-Modify-Write se- quence in which the current status from the CTR0 and CTR1 registers is ORed or AND- ed with the designated value and then written back into the registers. Example: When the status of bit 5 is 1, a timer reset condition occurs. Table 35. Counter/Timer 8 Control Register (CTR0) Bit 7 6 5 4 3 2 1 0 Field T8_Enable Single/ Modulo-N Time_Out T8 _Clock Capture_INT_M ask Counter_INT_M ask P34_Out Reset 0 00 0 0 0 00 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address Bank D: 00h; Linear: D00h Bit Position Value Description [7] 0 1 T8_EnableDisable/enable the T8 counter. Disable counter. Enable counter. Configure T8 properly before enabling it. [6] 0 1 Single Pass/Modulo-N MODULO-N mode. Counter reloads the initial value when terminal count is reached Single-Pass mode. Counter stops when the terminal count is reached [5] Read: 0 1 Write: 0 1 Time_OutThis bit is set when the T8 terminal count is reached. No counter time-out occurs. Counter time-out occurred. No effect. Reset flag to 0. Software must reset this flag before using counter/timers. Caution: Note: |
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