PCE85176AUGSLASHDA datasheet(27/48 Pages) NXP

27 / 48 page

PCE85176AUG

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Product data sheet

Rev. 1 — 12 January 2015

27 of 48

NXP Semiconductors

PCE85176AUG

4 × 40 LCD segment driver for Chip-On-Glass

8.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge

cycle.

• A slave receiver, which is addressed, must generate an acknowledge after the

reception of each byte.

• A master receiver must generate an acknowledge after the reception of each byte that

has been clocked out of the slave transmitter.

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be considered).

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgement on the I2C-bus is illustrated in Figure 20.

8.5 I2C-bus controller

The PCE85176AUG acts as an I2C-bus slave receiver. It does not initiate I2C-bus

transfers or transmit data to an I2C-bus master receiver. The only data outputs from the

PCE85176AUG are the acknowledge signals.

Fig 19. System configuration

Fig 20. Acknowledgement of the I2C-bus

PCE85176AUG/DA Datasheet(PDF) 27 Page - NXP Semiconductors