ST25R3911B datasheet(108/116 Pages) STMICROELECTRONICS

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Revision history

Table 105. Document revision history

Date

Revision

Changes

26-Sep-2016

Initial release.

16-Dec-2016

Updated document title, and image on cover page

Updated Features and Description.

Updated Section 1 Functional overview, Section 1.1.1 Transmitter, Section 1.1.2 Receiver,

Section 1.1.3 Phase and amplitude detector, Section 1.1.5 Capacitive sensor, Section

1.1.7 Quartz crystal oscillator, Section 1.1.8 Power supply regulators, Section 1.1.9 POR

and Bias, Section 1.1.10 RC oscillator and Wake-Up timer, Section 1.2.2 Transmitter,

Demodulation stage, Filtering and gain stages, Digitizing stage, Squelch, Receiver in NFCIP-1

active communication mode, Section 1.2.5 Wake-up mode, Auto-averaging, Section

1.2.8 A/D converter, Section 1.2.12 Communication with an external microcontroller and

Section 4.1 QFN32 package information.

Added Section 1.2.13 Direct commands.

Updated Table 11. Register preset bits, Table 18. Registers map. Table 19. IO configuration

Table 35. Auxiliary definition register, Table 37. Receiver configuration register 2,

Table 38. Receiver configuration register 3, Table 43. General purpose and no-response timer

control register, Table 47. Mask main interrupt register, Table 48. Mask timer and NFC

interrupt register, Table 49. Mask error and wake-up interrupt register, Table 52. Error and

wake-up interrupt register, Table 54. FIFO status register 2, Table 55. Collision display

control register, Table 65. RFO AM modulated level definition register, Table 66. RFO normal

level definition register, Table 67. External field detector threshold register,

Table 70. Regulator voltage control register, Table 71. Regulator and timer display register,

Table 73. RSSI display register, Table 78. Auxiliary display register, Table 81. Amplitude

measurement configuration register, Table 85. Phase measurement configuration register,

Table 93. IC identity register, Table 96. Electrostatic discharge, Table 101. Electrical

specifications and Section 5 Ordering information.

Removed footnote from Table 31. Minimum TR1 codings.

Updated Figure 4. Receiver block diagramin Section 1.2.3 Receiver, figure

Figure 8. ST25R3911B power supply, Section 1.2.12 Communication with an external

microcontroller, Section 1.2.13 Direct commands, Section 1.2.21 Antenna tuning and

Figure 32. QFN32 package outline.

19-Jul-2017

Updated Features, Description, Clear, FIFO water level and FIFO status registers, and

Section 1.2.15 Test access and Section 1.3.62 IC identity register.

Updated , Table 6. SPI operation modes, Table 9. Direct commands, Table 17. Setting mod

bits, Table 54. FIFO status register 2 and its footnotes, Table 74. RSSI and Table 93. IC

identity register and Table 101. Electrical specifications.

26-Feb-2018

Updated Table 2. Low pass controlTable 6. SPI operation modes, Table 9. Direct commands

and Table 27. ISO14443A and NFC 106kb/s settings register

Updated Example and Table 93. IC identity register.

Updated title and note of Section 5 Ordering information.

28-Jan-2019

Updated:

•

Table 4. Recommended blocking capacitor values

Added:

•

Table 14. FeliCa™ frame format

16-Apr-2020

Updated:

•

Figure 2. Minimum configuration with single sided antenna driving (including EMC filter)

Added:

•

Section 4.2 VFQFPN32 package information

ST25R3911B

DS11793 - Rev 6

page 108/116

ST25R3911B Datasheet(PDF) 108 Page - STMicroelectronics

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