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ST25R3911B Datasheet(PDF) 11 Page - STMicroelectronics |
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ST25R3911B Datasheet(HTML) 11 Page - STMicroelectronics |
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11 / 116 page ![]() RSSI The receiver also performs the RSSI (Received Signal Strength Indicator) measurement for both channels. The RSSI measurement is started after the rising edge of rx_on. It stays active as long as signal rx_on is high, it is frozen while rx_on is low. The RSSI is a peak hold system, and the value can only increase from the initial zero value. Every time the AGC reduces the gain the RSSI measurement is reset and starts from zero. Result of RSSI measurements is a 4-bit value that can be observed by reading the RSSI display register. The LSB step is 2.8 dB, and the maximum code is Dh (13d). Since the RSSI measurement is of peak hold type the RSSI measurement result does not follow any variations in the signal strength (the highest value will be kept). In order to follow RSSI variations it is possible to reset the RSSI bits and restart the measurement by sending the direct command Clear RSSI. Receiver in NFCIP-1 active communication mode There are several features built into the receiver to enable reliable reception of active NFCIP-1 communication. All these settings are automatically preset by sending the direct command Analog Preset after the NFCIP-1 mode has been configured. In addition to the filtering options, there are two NFCIP-1 active communication mode specific configuration bits stored in the Receiver configuration register 3. Bit lim enables clipping circuits that are positioned after the first and second gain stages. The function of the clipping circuits is to limit the signal level for the following filtering stage (when the NFCIP-1 peer is close the input signal level can be quite high). Bit rg_nfc forces gain reduction of second and third filtering stage to -6 dB while keeping the digitizer comparator window at maximum level. 1.2.4 Capacitive sensor The Capacitive sensor block (Figure 5) gives the possibility of low power detection of tag presence. The capacitive measurement system comprises two electrodes. One is the excitation electrode emitting an electrical field of a fixed frequency in the range of a few hundred kHz (CSO) and the second one is the sensing electrode (CSI). The amount of charge generated in the sensing electrode represents the capacitance between the two electrodes. The capacitive sensor electrodes are tolerant to parasitic capacitance to ground (up to 25 pF) and to input leakage (up to 1 MΩ). Since the charge on the sensing electrode is generated with the frequency of the excitation electrode, a synchronous rectifier is used to detect it. This ensures good rejection of interference and high tolerance to parasitic capacitances (to all nodes except the excitation electrode). The synchronous rectifier output is a DC voltage linearly proportional to the capacitance between the excitation and sensing electrode. The output DC voltage is converted by the A/D converter in absolute mode. The result is stored in the Section 1.3.33 A/D converter output register (see also Section 1.2.8 A/D converter). Figure 5. Capacitive sensor block diagram Oscillator A/D converter Synchronous rectifier CSO CSI Any conductive object (human hand or tag antenna windings) approaching the two electrodes changes the capacitance between the excitation and sensing electrode as it 'shortens' the distance between the two by providing conductance on the part of the path between the two electrodes. ST25R3911B Application information DS11793 - Rev 6 page 11/116 |
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