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ST25R3911B Datasheet(PDF) 38 Page - STMicroelectronics |
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ST25R3911B Datasheet(HTML) 38 Page - STMicroelectronics |
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38 / 116 page  Figure 21. ISO14443A states for PCD and PICC Standby Poll for PICC with REQA Receive ATQA Increase Cascade level ISO 14443-4 Check SAK Perform bit frame anticollision loop Power off (no field) ISO 14443-4 Idle (field ON) Ready Active PICC states PCD states UID not complete UID complete and PICC compliant with ISO 14443-4 Setting up the ST25R3911B for ISO 14443A anticollision To set up the ST25R3911B for the ISO14443A anticollision follow the steps indicated below. 1. The Initiator operation mode of ST25R3911B must be set up for ISO 14443A in the Mode definition register (default is already for ISO14443A). 2. The Tx and Rx bit rates must be set to default (106 kbps) in the Bit rate definition register. 3. Set the antcl bit in the ISO14443A and NFC 106kb/s settings register. This needs to be set before sending the REQA (or WUPA). As a result, the ST25R3911B will not trigger a framing error if in case the collision occurs in the ATQA or during anticollision procedure. Note: This bit must be set to one for REQA, WUPA and ANTOCOLLISION commands, for other commands it has to be zero. 4. Review and set a value for Mask receive timer register lower than the Frame delay time, as required by the ISO14443A, and set the No-response timer register 1 and Section 1.3.17 No-response timer register 2 according to the requirements. This is typically larger than the FDT. Note: The ST25R3911B offers the resolution of n/2 (64/fc - half steps) compared to n (128/fc) as mentioned in ISO 14443A so that the receiver can be unmasked n/2 steps before the actual transmission from the PICC. ST25R3911B Application information DS11793 - Rev 6 page 38/116 |
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