ST25R3911B datasheet(4/116 Pages) STMICROELECTRONICS

4 / 116 page

1.1.8

Power supply regulators

Integrated power supply regulators ensure a high power supply rejection ratio for the complete reader system. If

the reader system PSRR has to be improved, the command Adjust Regulators is sent. As a result of this

command, the power supply level of VDD is measured in maximum load conditions and the regulated voltage

reference is set 250 mV below this measured level to assure a stable regulated supply. The resulting regulated

voltage is stored in the Regulator and timer display register. It is also possible to define regulated voltage by

writing to the Regulator voltage control register. To decouple any noise sources from different parts of the IC there

are three regulators integrated with separated external blocking capacitors (the regulated voltage of all of them is

the same in 3.3 V supply mode). One regulator is for the analog blocks, one for the digital blocks, and one for the

antenna drivers.

This block additionally generates a reference voltage for the analog processing (AGD - analog ground). This

voltage also has an associated external buffer capacitor.

1.1.9

POR and Bias

This block provides the bias current and the reference voltages to all other blocks. It also incorporates a Power on

Reset (POR) circuit that provides a reset at power-up and at low supply voltage levels.

1.1.10

RC oscillator and Wake-Up timer

The ST25R3911B includes several possibilities of low power detection of card presence (capacitive sensor, phase

measurement, amplitude measurement). The RC oscillator and the register configurable Wake-Up timer are used

to schedule the periodic card presence detection.

1.1.11

ISO-14443 and NFCIP-1 framing

This block performs framing for receive and transmit according to the selected ISO mode and bit rate settings.

In reception it takes the demodulated sub-carrier signal from the receiver. It recognizes the SOF, EOF and data

bits, performs parity and CRC check, organizes the received data in bytes and places them in the FIFO.

During transmit, it operates inversely, it takes bytes from the FIFO, generates parity and CRC bits, adds SOF and

EOF and performs final encoding before passing the modulation signal to the transmitter.

In Transparent mode, the framing and FIFO are bypassed, the digitized sub-carrier signal (the receiver output), is

directly sent to the MISO pin, and the signal applied to the MOSI pin is directly used to modulate the transmitter.

1.1.12

FIFO

The ST25R3911B contains a 96-byte FIFO. Depending on the mode, it contains either data that has been

received or data to be transmitted.

1.1.13

Control logic

The control logic contains I/O registers that define operation of device.

1.1.14

SPI

A 4-wire Serial Peripheral Interface (SPI) is used for communication between the external microcontroller and the

ST25R3911B.

ST25R3911B

Block diagram

DS11793 - Rev 6

page 4/116

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