SPC58NH84C3 datasheet(101/147 Pages) STMICROELECTRONICS

Part #	SPC58NH84C3

Description	SPC58 H Line - 32 bit Power Architecture automotive MCU Triple z4 cores 200 MHz, 10 MBytes Flash, HSM, ASIL-D

PDF	147 Pages

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

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101 / 147 page

DS12304 Rev 5

101/147

SPC58EHx, SPC58NHx

Electrical characteristics

109

Figure 36. RMII transmit signal timing diagram

4.16.3.8

RGMII signal timing

The RGMII interface uses Double Data Rate (DDR) data transfer scheme; it requires that

the clock signal is delayed against the data and control signals.

This RGMII interface is compliant with the delay mode Delay on Source (DoS), where the

transmitter device already provides a delayed clock signal.

For detailed AC specifications, refer to chapter 7.3 “Signal timing parameters in DoS mode”

of specification “OPEN Alliance RGMII EPL (Electrical-Physical Layer) Recommendations”

standard v2.3.

4.16.4

FlexRay timing

This section provides the FlexRay Interface timing characteristics for the input and output

signals.

These are recommended numbers as per the FlexRay EPL v3.0 specification, and subject

to change per the final timing analysis of the device.

Table 53. RMII transmit signal timing

Symbol

Characteristic

Value

Unit

Min

Max

CC D REF_CLK to TXD[1:0], TX_EN invalid

—

CC D REF_CLK to TXD[1:0], TX_EN valid

—

CC D REF_CLK pulse width high

35%

65%

REF_CLK period

CC D REF_CLK pulse width low

35%

65%

REF_CLK period

REF_CLK (input)

TXD[1:0] (outputs)

TX_EN

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