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SPC58NH84C3 Datasheet(PDF) 14 Page - STMicroelectronics

Part # SPC58NH84C3
Description  SPC58 H Line - 32 bit Power Architecture automotive MCU Triple z4 cores 200 MHz, 10 MBytes Flash, HSM, ASIL-D
PDF  147 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPC58NH84C3 Datasheet(HTML) 14 Page - STMicroelectronics

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Description
SPC58EHx, SPC58NHx
14/147
DS12304 Rev 5
VLAN tag-based: Perfect match and Hash-based filtering. Filtering based on
either outer or inner VLAN tag is possible.
Layer 3 and Layer 4-based: TCP or UDP over IPv4 or IPv6
Extended VLAN tag based filtering with 16 filters
– IEEE 802.1Q VLAN tag detection
–
DMA block features:
– 64-bit data transfers
– 2-channel Transmit and Receive engines
– Separate DMA channel in the Transmit path for each queue
– Single or multiple DMA channels for any number of queues in Receive path
– Optimization for packet-oriented DMA transfers with packet delimiters
– Byte-aligned addressing for data buffer support
– Dual-buffer (ring) descriptor support
– Descriptor architecture to allow large blocks of data transfer with minimum
CPU intervention (each descriptor can transfer up to 32 KB of data)
–
Audio and video features:
Ethernet0 can be used in Audio Video (AV) mode, and the supported features are
compliant to the industry standards for AV traffic:
– Separate channels or queues for AV data transfer in 100 Mbps
– Up to 2- queues on the Receive paths for AV traffic and 1-queue on the
Transmit path for AV traffic
– IEEE 802.1-Qav specified credit-based shaper (CBS) algorithm for Transmit
channels
•
One ethernet controller 10/100/1000 Mbps (Ethernet 1)
Features changes on top of Ethernet 0:
–
RGMII PHY interface with DoS on TX clock
–
Transaction layer supports 3-TX queues and 3 RX queues
–
DMA supports 3 TX and 3-RX channels
–
Checksum offload engine on TX Queue0 only
–
16 KB each for both TX and RX FIFOs
–
2 AV queues on TX and 3 AV queues on RX
–
MAC does not support half duplex operations
–
Flexible Receive Parsing based filtering mode:
Programmable lookup table based flexible Parser for filtering all incoming packets
as per the programmable instructions in the memory. partial/group DA/SA match
(bit mask instead of byte mask). partial/group VLAN match (Only perfect match in
fixed/register filter) link DA/SA filter with VLAN filter; fixed/register filter does not
give that flexibility (sequential links) can do any of the fixed/register filter functions;



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