AD4697BCPZ datasheet(36/107 Pages) AD

36 / 107 page

Data Sheet

AD4697/AD4698

THEORY OF OPERATION

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Rev. 0 | 36 of 107

reference buffer is disabled and the REF input is driven directly,

AVDD can be as low as REF – 0.25 V. When the internal reference

buffer is enabled and VREF is provided on REFIN, AVDD must be at

least REFIN + 0.3 V (see Table 1).

VDD is nominally 1.8 V, and powers both the ADC core and the

device register memory. When power is first applied to VDD, the

ADC core initializes and the device register contents are set to the

default states (as shown in the Register Information section).

VIO can range from 1.14 V to 1.98 V and sets the input and output

levels for the digital interface pins. VIO allows direct interfacing with

digital controller logic levels between 1.2 V and 1.8 V (see the

Digital Interface section for more information).

Decouple AVDD, LDO_IN, VDD to AGND, and VIO to IOGND

with at least 100 nF. When shorting AVDD and LDO_IN, a single

decoupling capacitor can be used for both pins. When not using the

internal LDO, LDO_IN does not require decoupling.

As described in the Internal LDO section, the internal LDO requires

a decoupling capacitor of at least 100 nF on the VDD pin for proper

device operation.

The AD4697/AD4698 are independent of the power supply se-

quencing between VIO, VDD, and AVDD (and LDO_IN when the

internal LDO is enabled). When VIO and VDD are first supplied,

a power-on reset (POR) initiates (see the Device Reset section).

Additionally, the AD4697/AD4698 are insensitive to power supply

ripple over a wide frequency range, as shown in Figure 35.

Internal LDO

To minimize the number of system supply rails required to power

the AD4697/AD4698, the internal LDO can be used to supply the

VDD voltage internally. LDO_IN can be tied to AVDD to enable a

single supply to power the entire device (excluding VIO, which must

be powered by the digital host input/output voltage).

To enable the internal LDO, LDO_IN must be driven to at least

2.4 V, and VIO must already be powered. To enable the internal

LDO, set the LDO_EN bit in the setup register to 1. The internal

LDO is enabled by default on device power-up and after device

resets.

The output of the internal LDO is connected to the VDD pin.

When the internal LDO is enabled, its output drives VDD internally.

When the internal LDO is disabled, its output is disabled and high

impedance.

The internal LDO requires an output decoupling capacitor. When

using the internal LDO, include a 100 nF to 10 μF decoupling

capacitor between the VDD and AGND pins, as pictured in

Figure 112.

It is not possible to power the VIO supply with the internal LDO

output. VIO must be supplied by the digital host or other system

supply rail.

When using the internal LDO, the VDD supply voltage is driven by

the internal LDO output automatically when LDO_IN and VIO are

supplied. When not using the internal LDO, LDO_IN must be tied to

AGND, and VDD must be supplied externally.

The internal LDO output is designed to withstand being powered

up with VDD either driven by a separate 1.8 V supply or inadver-

tently shorted to AGND. It is recommended to ensure that VDD

is disconnected from any other rails or loads. The internal LDO

is not intended to power additional devices. It is recommended to

clear the LDO_EN bit of the setup register when powering VDD

externally, even if the LDO_IN input is shorted to AGND (see the

Device Configuration Recommendations section).

The internal LDO can be disabled to put the AD4697/AD4698 in a

low power state without disabling the AVDD, LDO_IN, or VIO rails.

When the internal LDO is disabled while VDD is not powered by

an external supply, the ADC core shuts down, and the configuration

again either with a wake-up command over the SPI, or with a

hardware reset. The wake-up command is 0x81 and is identical

to performing a software reset (see the Device Reset section for

detailed descriptions of hardware and software resets). The digital

interface requires that VIO still be supplied to accept the wake-up

command, and the internal LDO is not enabled if VIO is not within

the specified range (see Table 1).

OVERSAMPLING AND DECIMATION

The AD4697/AD4698 include an oversampling and decimation en-

gine that averages consecutive ADC samples to generate an over-

sampled result with higher effective resolution and lower effective

noise (see Table 1).

Each analog input channel can be configured with an OSR of 1, 4,

16, or 64. Conversion results generated for channels with an OSR

of 4, 16, or 64 are 17 bits, 18 bits, or 19 bits long, as shown in

Table 21 and Table 22 and the Transfer Function section.

When a given analog input channel is selected by the channel

sequencing logic, the multiplexer continues to select that channel

until the specified number of conversions have been performed,

and the results of each of those conversions are averaged together

to generate a single output code. For example, if IN0 is configured

with an OSR of 64, one averaged result is produced after the

64th consecutive CNV rising edge (when the AD4697/AD4698 are

in conversion mode). Configuring a channel with an OSR of 1 is

equivalent to performing no oversampling on that channel.

When enabled on the BSY_ALT_GP0 pin or the serial data out-

put(s), the busy indicator acts as a data ready signal, and only

transitions low when the oversampled result is available (see the

Busy Indicator section). Figure 78 shows the relative timing of the

busy indicator when the OSR for a channel is set to a value other

than 1.

The effective sample period of a given channel is equal to the

conversion period (tCYC) in Table 2 multiplied by its OSR. Figure 78

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