AD4697BCPZ datasheet(26/107 Pages) AD

26 / 107 page

Data Sheet

AD4697/AD4698

THEORY OF OPERATION

analog.com

Rev. 0 | 26 of 107

OVERVIEW

The AD4697/AD4698 are low power, 8-channel, 16-bit, 500 kSPS/

1 MSPS, multiplexed, precision SAR ADCs. The AD4697/AD4698

offer valid first conversion results even after being idle for long

periods of time.

The AD4697/AD4698 include features that simplify the design re-

quirements of peripheral circuitry and facilitate high performance

data acquisition system designs with low power consumption and

high channel density. These features include the following:

►

16-bit SAR ADC core with no missing codes

►

8 multiplexed analog inputs with low crosstalk multiplexer

►

Flexible channel sequencing modes

►

Analog input and reference high-Z mode

►

Internal reference buffer (WLCSP option only)

►

Temperature sensor

►

Input overvoltage protection clamps on each analog input

►

Programmable threshold detection for each analog input

►

Autocycle mode for performing conversions autonomously

►

First-order offset and gain correction for each analog input

►

Oversampling and decimation options for each analog input

When multiplexing between channels, the analog input high-Z

mode feature reduces the nonlinear voltage steps that occur at

the analog inputs. Analog input high-Z mode relaxes settling and

bandwidth requirements of the AFE circuitry and allows lower

bandwidth and lower power amplifiers to drive the analog inputs

directly.

The reference input high-Z mode feature significantly reduces the

REF input current while the ADC core performs conversions to

relax the drive requirements of the reference circuitry. This feature

allows the use of lower power references and smaller reference

decoupling capacitors (1 µF) than with traditional SAR ADCs.

The WLCSP option also includes an internal reference buffer with

high input impedance for directly interfacing with low power referen-

ces.

Each analog input is equipped with input overvoltage protection

clamps to protect the device from overvoltage events. The circuits

of the clamps are robust and prevent overvoltage events on an

analog input from significantly impacting the performance of the

other analog inputs.

The AD4697/AD4698 include a variety of channel sequencing

modes that provide a flexible means of performing conversions on

a sequence of analog input channels. The standard sequencer and

advanced sequencer allow a channel sequence to be preprogram-

med and automatically progressed as conversions occur. Two-cycle

command mode and single-cycle command mode allow the digital

host to manually select from the channels with SPI commands.

The AD4697/AD4698 have an enhanced digital interface that

is used to access the device register contents and initiate and

read conversion results while providing additional utility. Register

configuration mode is used to read and write to the register con-

tents. Conversion mode is used to initiate conversions and read

back conversion results. The fast conversion time of the AD4697/

AD4698 allows low serial clock rates to read back conversions even

when running at full throughput. The AD4697/AD4698 support the

4-wire SPI protocol and have optional dual- and quad-SDO modes

that enable slower SCK rates by shifting out conversion results on

multiple data outputs in parallel.

The power consumption of the AD4697/AD4698 scales

with throughput because the ADC core powers down between con-

versions. When operating at 10 kSPS, for example, the AD4697/

AD4698 typically consume 85 μW (with internal LDO, analog input

high-Z mode, reference high-Z mode and internal reference buffer

disabled), making the devices suitable for battery-powered applica-

tions.

The AD4697/AD4698 are available in a 24-lead, 4.00 mm ×

4.00 mm LFCSP or in a 36-lead, 2.960 mm × 2.960 mm WLCSP.

CONVERTER OPERATION

The AD4697/AD4698 contain an SAR-based ADC core that utilizes

a charge redistribution digital-to-analog converter (DAC) to quantize

the applied input voltage to an output code. Figure 63 shows a

simplified schematic of the AD4697/AD4698 SAR ADC core.

The analog inputs and the temperature sensor are connected to

the capacitor array inputs (ADCIN+ and ADCIN−) via the internal

low crosstalk multiplexer, represented by SWMUX+ and SWMUX− in

Figure 63. The multiplexer switches are controlled by the internal

channel sequencing logic and are updated once per conversion

(see the Multiplexer section and the Channel Sequencing Modes

section).

The AD4697/AD4698 SAR ADC conversion routine consists of an

acquisition phase and a conversion phase. The ADC remains in

the acquisition phase until the conversion phase begins. During the

acquisition phase, the capacitor array acquires the voltage on the

analog input channel selected by the internal multiplexer. During

the conversion phase, the ADC core samples the input voltage and

generates a corresponding output code result. Figure 64 shows the

data processing path for the conversion results generated by the

AD4697/AD4698 ADC core.

The AD4697/AD4698 must be in conversion mode to initiate the

conversion phase (see the Conversion Mode section). In register

configuration mode, the SAR ADC core remains in the acquisition

phase.

During the acquisition phase, the terminals of the capacitor array

tied to the input of the comparator are connected to REFGND

through the SW+ and SW− switches. All switches on the individual

capacitors in the array are connected to ADCIN+ and ADCIN−, and

ADCIN+ and ADCIN− are connected to the selected analog input

AD4697BCPZ Datasheet(PDF) 26 Page - Analog Devices

AD4697BCPZ Datasheet(HTML) 26 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL