7

I²C interface protocol

7.1

Write mode transmission

The LNBH26S interface protocol is made up of:

•

a start condition (S)

•

a chip address byte with the LSB bit R/W = 0

•

a register address (internal address of the first register to be accessed)

•

a sequence of data (byte to write in the addressed internal register + acknowledge)

•

the following bytes, if any, to be written in successive internal registers

•

a stop condition (P). The transfer lasts until a stop bit is encountered

•

the LNBH26S, as slave, acknowledges every byte transfer

S

0 0 0 1 0 0 X

0 0 0 0 0 X X X

MSB

LSB

CHIP ADDRESS

MSB

LSB

REGISTER ADDRESS

P

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

DATA 1

Add=0x2

DATA 2

Add=0x3

DATA 3

Add=0x4

DATA 4

Add=0x5

GIPG0202151231LM

ACK = acknowledge

S = start

P = stop

R/W = 1/0, read/write bit

X = 0/1, set the values to select the chip address (see Table 15. Address pin characteristics for pin selection)

Note:

The writing procedure can start from any register address by simply setting the X values in the register address

byte (after the chip address). It can be also stopped by the master by sending a stop condition after any

acknowledge bit.

7.2

Read mode transmission

In read mode the byte sequence must be as follows:

•

a start condition (S)

•

a chip address byte with the LSB bit R/W=0

•

the register address byte of the internal first register to be accessed

•

a stop condition (P)

•

a new master transmission with the chip address byte and the LSB bit R/W=1

•

after the acknowledge the LNBH26S starts sending the addressed register content. As long as the master

keeps the acknowledge LOW, the LNBH26S transmits the next address register byte content

LNBH26S

I²C interface protocol

DS8975 - Rev 5

page 16/35