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LNBH26S Datasheet(PDF) 20 Page - STMicroelectronics |
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LNBH26S Datasheet(HTML) 20 Page - STMicroelectronics |
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20 / 35 page ![]() Bit Name CH Value Description Bit 6 THERM A/B 1 If thermal protection is active (OTF=1), all VSEL bits are reset to “0” and LNB output (VOUT pin) is disabled (both section A and B). VSEL bits must be set again by the master after the overtemperature condition is removed (OTF=0) 0 In the case of thermal protection activation (OTF=1) the LNB output (VOUT pin) is automatically enabled as soon as the overtemperature condition is removed (OTF=0) with the previous VSEL bit setting Bit 7 (MSB) COMP 1 DC-DC converter compensation. Set to use very low E.S.R. capacitors or ceramic caps on VUP pin 0 DC-DC converter compensation. Set to use standard electrolytic capacitors on VUP pin 7.4 Status registers The STATUS 1, 2 registers can be addressed to read mode only and provide the diagnostic functions described in the following tables. Table 10. STATUS 1 (read register. Register address = 0X0) Bit Name CH Value Description Bit 0 (LSB) OLF-A A 1 VOUT pin overload protection has been triggered (IOUT > ILIM). 0 No overload protection has been triggered to VOUT pin (IOUT < ILIM) Bit 1 OLF-B B 1 VOUT pin overload protection has been triggered (IOUT > ILIM). 0 No overload protection has been triggered to VOUT pin (IOUT < ILIM) Bit 2 VMON-A A 1 Output voltage (VOUT pin) is lower than VMON specification thresholds. Refer to Table 16. Output voltage diagnostic (VMON-A/B bits, STATUS 1 register) characteristics 0 Output voltage (VOUT pin) is within the VMON specifications Bit 3 VMON-B B 1 Output voltage (VOUT pin) is lower than VMON specification thresholds. Refer to Table 16. Output voltage diagnostic (VMON-A/B bits, STATUS 1 register) characteristics 0 Output voltage (VOUT pin) is within the VMON specifications Bit 4 PDO-A A 1 Overcurrent detected on output pull-down stage for a time longer than the deglitch period. This may happen due to an external voltage source present on the LNB output (VOUT pin) 0 No overcurrent detected on output pull-down stage Bit 5 PDO-B B 1 Overcurrent detected on output pull-down stage for a time longer than the deglitch period. This may happen due to an external voltage source present on the LNB output (VOUT pin) 0 No overcurrent detected on output pull-down stage LNBH26S Status registers DS8975 - Rev 5 page 20/35 |
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