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SH79F085M/024MU Datasheet(PDF) 96 Page - SINOWEALTH Electronic Ltd |
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SH79F085M/024MU Datasheet(HTML) 96 Page - SINOWEALTH Electronic Ltd |
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96 / 97 page ![]() SH79F085/SH79F165 96 Content 1. FEATURES .....................................................................................................................................................................1 2. GENERAL DESCRIPTION..............................................................................................................................................1 3. BLOCK DIAGRAM ..........................................................................................................................................................2 4. PIN CONFIGURATION ...................................................................................................................................................3 5. PIN DESCRIPTION.........................................................................................................................................................6 6. SFR MAPPING................................................................................................................................................................8 7. NORMAL FUNCTION ...................................................................................................................................................15 7.1 CPU .................................................................................................................................................................................................... 15 7.1.1 CPU Core SFR ............................................................................................................................................................................ 15 7.1.2 Enhanced CPU core SFRs........................................................................................................................................................... 16 7.1.3 Register........................................................................................................................................................................................ 16 7.2 RAM ................................................................................................................................................................................................... 17 7.2.1 Feature ........................................................................................................................................................................................ 17 7.2.2 Register........................................................................................................................................................................................ 17 7.3 FLASH PROGRAM MEMORY .................................................................................................................................................................. 18 7.3.1 Feature ........................................................................................................................................................................................ 18 7.3.2 Flash Operation in ICP Mode ..................................................................................................................................................... 20 7.3.3 Flash Download in ISP Mode...................................................................................................................................................... 20 7.4 SSP FUNCTION..................................................................................................................................................................................... 21 7.4.1 SSP Register ................................................................................................................................................................................ 21 7.4.2 Flash Control Flow...................................................................................................................................................................... 24 7.4.3 SSP Programming Notice ............................................................................................................................................................ 25 7.5 SYSTEM CLOCK AND OSCILLATOR........................................................................................................................................................ 26 7.5.1 Feature ........................................................................................................................................................................................ 26 7.5.2 Clock Definition........................................................................................................................................................................... 26 7.5.3 Description .................................................................................................................................................................................. 26 7.5.4 Register........................................................................................................................................................................................ 27 7.5.5 Oscillator Type ............................................................................................................................................................................ 28 7.5.6 Capacitor selection for Oscillator ............................................................................................................................................... 29 7.6 SYSTEM CLOCK MONITOR (SCM) ........................................................................................................................................................ 30 7.7 I/O PORT.............................................................................................................................................................................................. 31 7.7.1 Feature ........................................................................................................................................................................................ 31 7.7.2 Register........................................................................................................................................................................................ 31 7.7.3 Port Diagram............................................................................................................................................................................... 32 7.7.4 Port Share.................................................................................................................................................................................... 33 7.8 TIMER .................................................................................................................................................................................................. 36 7.8.1 Feature ........................................................................................................................................................................................ 36 7.8.2 Timer0/1 ...................................................................................................................................................................................... 36 7.8.3 Timer2 ......................................................................................................................................................................................... 41 7.8.4 Timer3 ......................................................................................................................................................................................... 47 7.9 INTERRUPT........................................................................................................................................................................................... 49 7.9.1 Feature ........................................................................................................................................................................................ 49 7.9.2 Interrupt Enable Control ............................................................................................................................................................. 49 7.9.3 Register........................................................................................................................................................................................ 49 7.9.4 Interrupt Flag .............................................................................................................................................................................. 51 7.9.5 Interrupt Vector ........................................................................................................................................................................... 53 7.9.6 Interrupt Priority ......................................................................................................................................................................... 53 7.9.7 Interrupt Handling....................................................................................................................................................................... 54 7.9.8 Interrupt Response Time.............................................................................................................................................................. 54 7.9.9 External Interrupt Inputs ............................................................................................................................................................. 55 7.9.10 Interrupt Summary..................................................................................................................................................................... 55 8. ENHANCED FUNCTION...............................................................................................................................................56 8.1 REGULATOR......................................................................................................................................................................................... 56 8.1.1 Feature ........................................................................................................................................................................................ 56 8.1.2 Regulator ..................................................................................................................................................................................... 56 8.2 ENHANCED UNIVERSAL ASYNCHRONOUS RECEIVER-TRANSMITTER (EUART) ..................................................................................... 57 8.2.1 Feature ........................................................................................................................................................................................ 57 8.2.2 EUART Mode Description ........................................................................................................................................................... 57 8.2.3 Baud Rate Generate..................................................................................................................................................................... 62 8.2.4 Multi-processor Communication ................................................................................................................................................. 62 8.2.5 Error Detection............................................................................................................................................................................ 64 |
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