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TDA7803A-QLX Datasheet(PDF) 45 Page - STMicroelectronics |
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TDA7803A-QLX Datasheet(HTML) 45 Page - STMicroelectronics |
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45 / 72 page ![]() DS12195 Rev 7 45/72 TDA7803A I2C bus interface 71 9.7 Address selection To select the proper I2C address a resistor must be connected to ADD pin as follows: 9.8 I2C bus timings This paragraph describes more in detail the I2C bus protocol used and its timings. Figure 45 and Table 15 include the timings that have to be respected in order to correctly write into/ read from the I2C registers. Figure 45. I2C bus interface timing Table 14. Address threshold ADD2 ADD1 Rload 0 0 120K < R 0 1 56K < R < 64K 1 0 30K < R < 38K 1 1 R < 15K Table 15. I2C bus interface timing Symbol Parameter Min Max Unit Fscl SCL (clock line) frequency - 400 kHz Tscl SCL period 2500 - ns Tsclh SCL high time 0.6 - µs Tscll SCL low time 1.3 - µs Tsstart Setup time for start condition 0.6 - µs Thstart Hold time for start condition 0.6 - µs Tsstop Setup time for stop condition 0.6 - µs Tbuf Bus free time between a stop and a start condition 1.3 - µs Tssda Setup time for data line 100 - ns Thsda Hold time for data line 0(1) 1. Device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL. -ns Tf Fall time for SCL and SDA - 300 ns GAPGPS00814 Tbuf SCL SDA MSB7 MSB0 ACK Tsstart start Thstart Tssda Thsda Tsclp Tsstop stop Tscll Tsclh |
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