L9788 datasheet(52/264 Pages) STMICROELECTRONICS

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Watchdog

L9788

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DS12308 Rev 4

4.1.4

Question generation

The generation of the 4-bit question (REQU[3-0]) is realized as in the table below. The 4-bit

counter only changes to the next state during the sequencer-run when the previous

question has been answered correctly in value and in time. The state is changed by a

sequencer-run because of a write-access to the RESPTIME register or the expiration of the

time window.

When RST_UV is active the state is set to 0000b

4.1.5

Response comparison

The 2-bit counter <RESP_CNT (1-0)> counts the received bytes of the 32-bit response and

controls the generation of the expected response. Its default value is "11" (corresponds to

"waiting for RESP_BYTE3").

The <RESP_ERR> flag is set '1' when a response byte is incorrect. The flag remains '0' if

the 32-bit response is correct. The ERROR COUNTER is updated with the flag. The default

state of the flag is '0'.

The 2-bit counter <RESP_CNT (1-0)> and the <RESP_ERR> flag are reset to their

corresponding default values at a sequencer-run. The reset condition of the counter

<RESP_CNT (1-0)> and the <RESP_ERR> flag are the corresponding default states.

Procedure of the sequential response comparison:

<RESP_CNT (1-0)> = "11": switch the expected response for RESP_BYTE3 to the

comparator

Write access: RESP_BYTE3

Set <RESP_CNT> to "10", update <RESP_ERR> flag

<RESP_CNT (1-0)> = "10": switch the expected response for RESP_BYTE2 to the

comparator

Write access: RESP_BYTE2

set <RESP_CNT> to "01", update <RESP_ERR> flag

<RESP_CNT (1-0)> = "01": switch the expected response for RESP_BYTE1 to the

comparator

Write access: RESP_BYTE1

set <RESP_CNT> to "00", update <RESP_ERR> flag

<RESP_CNT (1-0)> = "00": switch the expected response for RESP_BYTE0 to the

comparator

"update <RESP_ERR> flag" previously described means that it sets <RESP_ERR> flag to 1

if a response byte is incorrect. Once <RESP_ERR> flag is set to 1 it maintains its value until

next sequencer run.

Write access: RESP_BYTE0

Start sequencer (SEQU_START signal), set <RESP_CNT> to "11", update <RESP_ERR>

flag, update ERROR COUNTER

Sequencer clears <RESP_ERR> flag to '0

SEQU_START = (RESP_CNT1=0) AND RESP_CNT0=0) AND "response byte write"

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