L9788 datasheet(172/264 Pages) STMICROELECTRONICS

172 / 264 page

Built in self test

L9788

172/264

DS12308 Rev 4

will cause the loss of monitor functionality with an undetected latent fault; the insertion of a

monitor supplied from V3V3PRE and referenced to VBG1 allows the detection of this latent.

The same concept applies on the vice-versa.

The remaining common points of the internal architecture can be summarized as:



protected battery line,



charge pump supply,



V3V3PRE_mon monitor input (netA),



V3V3PRE monitor input (netB)

The above points can be tolerated because:



Protected battery line is the main supply of the L9788, used to generate supply for

analog and digital core. All the circuits connected to this rail are capable of high voltage

operation, in case the connection is lost no logic supply can be generated and the

device will be stuck in reset condition.



Charge pump is used to guarantee proper functionality during battery cranking only

and is useless in normal mode. All the circuits connected to this line are capable of high

voltage, in case the line is open it can be detected by dedicated monitor (not shown

here) during normal operation or at power-up of the device.



In case netA is shorted to ground there is fault detection while short to supply line is

normal condition, short to VBG1 through V3V3PRE_mon monitor inputs is not possible

since the inputs are cascaded; in case a double fault is present (shorted cascade) it will

cause an increase in analog and digital supply lines (VINT3V3 and VDD2V7) detected

by their monitors using VBG2 reference and triggering safety switch-off path for safety

relevant outputs.



In case netB is shorted to ground there is fault detection while short to supply line is

normal condition, short to VBG2 through V3V3PRE monitor inputs is not possible since

the inputs are cascaded; in case a double fault is present (shorted cascade) it will

cause a failure on the monitor circuit only, without affecting normal functionality until a

third fault occurs.

14.2

Analog comparators BIST

For all the safety relevant monitors a self test is implemented to verify that the comparator

can detect a variation of the monitored signal applied at its input. The basic implementation

scheme is shown in Figure 80: comparator inputs are choppered by a diagnostic clock and

the output of the comparator is xored with diagnostic clock itself: if the comparator is not

able to toggle due to fault condition (internal or external) its output will start toggling

following diagnostic clock and causing a self test failure.

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