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L9788 Datasheet(PDF) 232 Page - STMicroelectronics |
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L9788 Datasheet(HTML) 232 Page - STMicroelectronics |
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232 / 264 page  Micro second channel (MSC) interface L9788 232/264 DS12308 Rev 4 18.6.12 Upstream Bit Map Read12 (PHOLD+POWER_UP+ADC) FRAME[1:2]: POWER_HOLD TIMER It is the counter used to reach the timeout selected by PHOLD_TIME[0:1] configuration bits. The run time is derived from the PHOLD_TIMER[14:0] according to the formula: run time = PHOLD_TIMER[14:0] * 279 ms FRAME[3]: POWER_UP [0] KEY_IN_DET Latch status of activation of KEY_IN signal 0: low level detected on KEY_IN signal 1: high level on KEY_IN signal [1] WK_IN_DET Latch status of activation of WK_IN signal. 0: no positive edge detected on WK_IN signal Table 104. MSC Interface Upstream Bit Map Read12 ADDRESS DATA A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7 FRAME1 0 0 0 0 PHOLD PHOLD _TIME STATUS PHOLD TIMER [0] PHOLD TIMER [1] PHOLD TIMER [2] PHOLD TIMER [3] PHOLD TIMER [4] PHOLD TIMER[5] PHOLD TIMER[6] FRAME2 0 0 1 0 PHOLD PHOLD TIMER [7] PHOLD TIMER [8] PHOLD TIMER [9] PHOLD TIMER [10] PHOLD TIMER [11] PHOLD TIMER [12] PHOLD TIMER [13] PHOLD TIMER [14] FRAME3 0 0 0 1 POWER UP EOT_ST ATUS ADC KEY_IN _DET WK_IN _DET WAKE_ UP_EO T_DET WAKE_ UP_CAN _DET FAULT_ WARN EOT(1) ADC[0] ADC[1] FRAME4 0 0 1 1 ADC ADC[2] ADC[3] ADC[4] ADC[5] ADC[6] ADC[7] ADC[8] ADC[9] source FRAME[1]D[0:7] FRAME[2]D[0:7] FRAME[3]D[0:4] FRAME[3]D[6:7] FRAME[4]D[0:7] logic on VB_IN (main logic) FRAME[3]D[5] logic on VB_STBY (Wake Up Timer logic) access read 1. Bit in satellite logic. |
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