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L9788 Datasheet(PDF) 248 Page - STMicroelectronics |
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L9788 Datasheet(HTML) 248 Page - STMicroelectronics |
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248 / 264 page  Device behavior L9788 248/264 DS12308 Rev 4 Figure 100. Main relay driver timeout Figure 101. Power HOLD According to reset matrix power down is also produced by Watchdog PWR_CNT counter overflow during KEY_IN low. In these cases the power down sequence is actuated without considering VDD5 undervoltage. GADG1512161238PS t ON SCENARIO 26 – Main Relay Driver Timeout RSTN VTRK VDD5 VPRE Power On Reset V3V3A/D VB_IN MRD out PHOLD WAKE_UP_CAN_DET WAKE_UP_EOT_DET WK_IN_DET MRD_EN_TIMEOUT (500ms typ) OFF OFF GADG1512161244PS KEY_IN_DET WK_IN_DET WAKE_UP_EOT_DET WAKE_UP_CAN_DET PHOLD MRD out VB_IN Power On Reset VPRE VDD5 VTRK RSTN t Note*: Power On Reset is activated at the end of power down sequence without waiting for VUV_VB_CP_OFF Td_uv_rst Vuv_vpre Vuv_vdd5 Tuv_filter_vdd5 Tuv_filter_vpre Vuv_vpre Vuv_vdd5 Tuv_filter_vdd5 Tuv_filter_vpre MSC_PHOLD_EN=0 or PHOLD_TIMEOUT V UV_VB_CP_OFF V UV_VB_IN SCENARIO 11 - POWER HOLD not permanent battery |
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