LSM6DSRX datasheet(164/171 Pages) STMICROELECTRONICS

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Table 106. EMB_FUNC_STATUS_MAINPAGE register ................................................ 70

Table 107. EMB_FUNC_STATUS_MAINPAGE register description ........................................ 70

Table 108. FSM_STATUS_A_MAINPAGE register .................................................... 71

Table 109. FSM_STATUS_A_MAINPAGE register description ............................................ 71

Table 110. FSM_STATUS_B_MAINPAGE register .................................................... 71

Table 111. FSM_STATUS_B_MAINPAGE register description ............................................ 71

Table 112. MLC_STATUS_MAINPAGE register ...................................................... 72

Table 113. MLC_STATUS_MAINPAGE register description .............................................. 72

Table 114. STATUS_MASTER_MAINPAGE register................................................... 72

Table 115. STATUS_MASTER_MAINPAGE register description .......................................... 72

Table 116. FIFO_STATUS1 register .............................................................. 73

Table 117. FIFO_STATUS1 register description ...................................................... 73

Table 118. FIFO_STATUS2 register .............................................................. 73

Table 119. FIFO_STATUS2 register description ...................................................... 73

Table 120. TIMESTAMP3 register ............................................................... 74

Table 121. TIMESTAMP2 register ............................................................... 74

Table 122. TIMESTAMP1 register ............................................................... 74

Table 123. TIMESTAMP0 register ............................................................... 74

Table 124. TAP_CFG0 register ................................................................. 75

Table 125. TAP_CFG0 register description ......................................................... 75

Table 126. TAP_CFG1 register ................................................................. 76

Table 127. TAP_CFG1 register description ......................................................... 76

Table 128. TAP priority decoding ................................................................ 76

Table 129. TAP_CFG2 register ................................................................. 76

Table 130. TAP_CFG2 register description ......................................................... 76

Table 131. TAP_THS_6D register ............................................................... 77

Table 132. TAP_THS_6D register description ....................................................... 77

Table 133. INT_DUR2 register.................................................................. 77

Table 134. INT_DUR2 register description ......................................................... 77

Table 135. WAKE_UP_THS register.............................................................. 78

Table 136. WAKE_UP_THS register description ..................................................... 78

Table 137. WAKE_UP_DUR register ............................................................. 78

Table 138. WAKE_UP_DUR register description ..................................................... 78

Table 139. FREE_FALL register ................................................................ 79

Table 140. FREE_FALL register description ........................................................ 79

Table 141. MD1_CFG register .................................................................. 80

Table 142. MD1_CFG register description.......................................................... 80

Table 143. MD2_CFG register .................................................................. 81

Table 144. MD2_CFG register description.......................................................... 81

Table 145. S4S_ST_CMD_CODE register ......................................................... 82

Table 146. S4S_ST_CMD_CODE register description ................................................. 82

Table 147. S4S_DT_REG register ............................................................... 82

Table 148. S4S_DT_REG register description ....................................................... 82

Table 149. I3C_BUS_AVB register ............................................................... 82

Table 150. I3C_BUS_AVB register description....................................................... 82

Table 151. INTERNAL_FREQ_FINE register........................................................ 83

Table 152. INTERNAL_FREQ_FINE register description................................................ 83

Table 153. INT_OIS register ................................................................... 84

Table 154. INT_OIS register description ........................................................... 84

Table 155. CTRL1_OIS register................................................................. 85

Table 156. CTRL1_OIS register description......................................................... 85

Table 157. DEN mode selection................................................................. 85

Table 158. CTRL2_OIS register................................................................. 86

Table 159. CTRL2_OIS register description......................................................... 86

LSM6DSRX

List of tables

DS13007 - Rev 3

page 164/171

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